Hello,My APB1 bus frequency is 21Mhz as shown in the clock diagram bellow.
I have the following code for timer delay shown in the photo bellow.
I have PSC register and ARR register to define the TIMER.
In timer we are counting up every clock tick up and ARR is the value where we are reseting the counting.
from the RM link shown bellow,We have other registers like CCR1,DIER,EGR.
I am trying to understand the logics of this registers.
I Cant find in the CR register the counter overflow interrupt option.
Where is it?
Thanks.
https://www.st.com/resource/en/refe...-arm-based-32-bit-mcus-stmicroelectronics.pdf
I have the following code for timer delay shown in the photo bellow.
I have PSC register and ARR register to define the TIMER.
In timer we are counting up every clock tick up and ARR is the value where we are reseting the counting.
from the RM link shown bellow,We have other registers like CCR1,DIER,EGR.
I am trying to understand the logics of this registers.
I Cant find in the CR register the counter overflow interrupt option.
Where is it?
Thanks.
https://www.st.com/resource/en/refe...-arm-based-32-bit-mcus-stmicroelectronics.pdf
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