Hi,
Which method would you use to pick the high frequency ceramic cap value for DC/DC input stage?
Suppose I know the current waveform at Fsw, and based on the inductance I know dI/dt too, I assumed that the HF cap should be chosen in a way to
maintain a small impedance at the correct knee frequency of the triangle waveform, in order that the current loop will be closed by this cap and not from the far electrolytic capacitor.
Any thoughts?

 

Hello there

Which method would you use to pick the high frequency ceramic cap value for DC/DC input stage?

I would not pick any of the methods you suggested.
A starting point is to select the key ceramic capacitors to meet the requirements for ripple voltage and current.
Due to DC bias capacitance degrading, the effective capacitance is not the same as the rated capacitance.
Since the equivalent series resistance (ESR) of ceramic capacitors is very low, ripple resulting from ESR can be ignored.
Besides the ripple-voltage requirement, the ceramic capacitors should meet the thermal stress requirement as well. A starting point is to estimate the maximum rootmean-square (RMS) of Δi IN_D.
the ratio of input ripple current RMS over load current (IIN_RMS/ILoad) as a function of the duty cycle.
the maximum input ripple current RMS occurs at full load and with duty cycle of 12.1%,
To alleviate input spikes and phase-node ringing
a high di/dt slope of the input current and highvoltage spike at the input and phase node. The ESL of the ceramic capacitors plays a significant role. Thus, it is desirable to further lower the input capacitor ESL. This can be achieved by adding a small capacitor with low ESL. Despite the fact that ESL varies with material and structure, a common rule of thumb is that a capacitor with a smaller case has a lower ESL