How do I EM-Extract a subcircuit and define a different em/drawing-layer than the original circuit in AWR?

Thread Starter

ewheeler

Joined Sep 9, 2020
4
I have a 4-layer project in AWR/MWOffice and have built a parameterized microstrip inductor schematic (named "spiral") with a "Line Type" of layer1 that I wish to reuse on another schematic as a subcircuit (SUBCKT) on layers 1,2,4.

When I place "spiral" as a subcircuit on another schematic ("sch1") and assign that SUBCKT shape's "Line Type" to be different than "spiral" was drawn, EM extraction puts it on the layer where "spiral" was drawn, not where the SUBCKT is drawn.

(By "drawn" I mean right-click the shape in Layout View, select Shape Properties, and select the "Line Type" in the "Layout" tab; I know my EM layer mappings are correct because I can change the line type of "spiral" and EM extraction puts it in that em-layer, but let me know if there is an LPF trick I should try since I can't get multiple SUBCKT's to extract into different layers).

Strangely, the drawing shape color/pattern that I assigned for layer1 always shows in "sch1" even though the SUBCKT element line-types are set to layers 1,2,4. However, if I right-click on each SUBCKT's shape properties, each SUBCKT's "Line Type" is shown correctly. Here are the details:
  • The microstrip schematic ("spiral") layout is all drawn on layer1
  • Another schematic ("sch1") has the following subcircuits:
    • SUBCKT S1: NET="spiral", shape layer=layer1
    • SUBCKT S2: NET="spiral", shape layer=layer2
    • SUBCKT S3: NET="spiral", shape layer=layer4

Is there a way to reuse my "spiral" subcircuit on different drawing layers so that it shows correctly both in the "Layout View" and is placed correctly in the EM extraction?

I've attached my LPF in case its useful. In the post above, "layer1" means Cu_1, and so-on. Let me know if there is anything else you might need to help troubleshoot.

Thank you for your help!

-Eric
 

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jpanhalt

Joined Jan 18, 2008
11,087
Welcome to AAC.

Your question seems very specific to Cadence software. While some users here may be familiar with that software, have you also checked on the Cadence community?
 

Thread Starter

ewheeler

Joined Sep 9, 2020
4
Thanks!

Do you have a link to the Cadence community? If there is a forum I'd like to post there.

(The forums that I did find now point at a support email, but my not-for-profit research license prohibits contacting support.)
 

Thread Starter

ewheeler

Joined Sep 9, 2020
4
Cross-linking in case someone finds my post, this is the answer on the Cadence Community forum:

https://community.cadence.com/caden...n-the-original-circuit-in-awr/1369415#1369415

What you are asking isn’t possible although the issue isn’t due to the extraction itself. The built-in microstrip models/pcells you are using read their drawing layer info from the linetypes section configured in the lpf, and which lpf linetype gets selected is controlled by either the MSUB name chosen on the corresponding model or the setting you manually select on the dropdown menu in the layout cell properties.

Case 1: If your MSUB definition names match the linetype names in the lpf, then when you select the appropriate MSUB definition for your line, the layout will pick the corresponding linetype used for layout automatically.

Case 2: If your MSUB definition names don’t match your linetype names then you need to manually set the correct drawing layer using the pulldown menu in the layout cell’s shape properties.

In either case, there is no way to pass this information down through the schematic hierarchy which is what you’d need to do in order to extract multiple copies of “spiral” on different linetypes from a single top level schematic. Standard parameters such as width, length, etc, can all be passed through hierarchy with ease, but MSUB and linetype are special cases which cannot.

The simplest work around for you is to just make 4 schematics, “spiral_Cu1”, “spiral_Cu2”, “spiral_Cu3”, and “spiral_Cu4” where the correct linetype is pre-set in each and then place them in your higher level design accordingly. Any of your usual geometrical parameters can still be passed to create different sized devices but the pcells you are reusing are not coded to accept drawing layer information passed through hierarchy in this way.

Best Regards,

Graeme
 
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