I lack the total understanding of the logic gate construction other then one being built internally with BJT and the other being built with with fets (CMOS)
Riddle me this, on a CMOS part say an AND gate i was just farting around with, i did the following.
Both inputs of the AND gate are just tied to ground on a bread board. I put a pull down on both of them of 100k
The initial state of the circuit is just false on both gates.
I tie them both to the bread board 5V and surprise, the gate outputs a true.
However, returning them both to ground does not shut it off or turn it false.
Upon further inspection, with the 100k pulldown, there is a mysterious 2V sitting at both gates. As if the inputs are actually sourcing 2V somehow.
Just for kicks, i tried a much smaller pulldown of 10k instead of 100k and it works as expected. This experiment has me paying more attention to pull down choices but i thought on a CMOS part it was not a concern like TTL
Can someone explain to me why this just happened? Thanks
Riddle me this, on a CMOS part say an AND gate i was just farting around with, i did the following.
Both inputs of the AND gate are just tied to ground on a bread board. I put a pull down on both of them of 100k
The initial state of the circuit is just false on both gates.
I tie them both to the bread board 5V and surprise, the gate outputs a true.
However, returning them both to ground does not shut it off or turn it false.
Upon further inspection, with the 100k pulldown, there is a mysterious 2V sitting at both gates. As if the inputs are actually sourcing 2V somehow.
Just for kicks, i tried a much smaller pulldown of 10k instead of 100k and it works as expected. This experiment has me paying more attention to pull down choices but i thought on a CMOS part it was not a concern like TTL
Can someone explain to me why this just happened? Thanks