I am playing with a project for making a sine wave inverter for low voltage. There is a very good TI paper talking about a reference design here:
http://www.ti.com/lit/an/slaa602a/slaa602a.pdf
However I dont really need to confine myself to 50Hz. So I thought it would be interesting to get to grips with some CPLD programming and VHDL so potentially allow much quicker speeds than with a microcontroller and lookup table.
Doing all the number crunching for the number of Duty cycle modulated pulses, ultimate clock speed (that makes up these pulses).. etc. it works out at a very great number of clock pulses. Ideally the resulting sine wave should be beyond audio frequency so there is no annoying buzzing, but I guess if you get much beyond 1uS on / off time (?) for the FETs your starting to get significant switching losses while the FET is actually trying to switch state.
So... any hard and fast guidelines for a good ball park minimum off / on time for your average power mosfet? Or other things Ive undoubtedly forgotten?!
http://www.ti.com/lit/an/slaa602a/slaa602a.pdf
However I dont really need to confine myself to 50Hz. So I thought it would be interesting to get to grips with some CPLD programming and VHDL so potentially allow much quicker speeds than with a microcontroller and lookup table.
Doing all the number crunching for the number of Duty cycle modulated pulses, ultimate clock speed (that makes up these pulses).. etc. it works out at a very great number of clock pulses. Ideally the resulting sine wave should be beyond audio frequency so there is no annoying buzzing, but I guess if you get much beyond 1uS on / off time (?) for the FETs your starting to get significant switching losses while the FET is actually trying to switch state.
So... any hard and fast guidelines for a good ball park minimum off / on time for your average power mosfet? Or other things Ive undoubtedly forgotten?!
