Hi all,
I have been given the task of creating a 16-bit synchronous counter out of two 3-bit, and two 5-bit counters. I have started the initial process of getting my circuit down on paper before I go off and get frustrated with the wonderful piece of software known as Xilinx. I have a quick question though. In the instructions it specifies to use a CLK and CE (I believe this was "clock enable" input) in my design. I would then have my Terminal Count as an output that would then be ANDed with the CE of my next counter in series. Now here is my question: Am I going to want to connect the CLK and CE both to the same input? But have my CE in my other counters (not my first one in series) ANDed with my Terminal Count coming from the first adder?
I have been given the task of creating a 16-bit synchronous counter out of two 3-bit, and two 5-bit counters. I have started the initial process of getting my circuit down on paper before I go off and get frustrated with the wonderful piece of software known as Xilinx. I have a quick question though. In the instructions it specifies to use a CLK and CE (I believe this was "clock enable" input) in my design. I would then have my Terminal Count as an output that would then be ANDed with the CE of my next counter in series. Now here is my question: Am I going to want to connect the CLK and CE both to the same input? But have my CE in my other counters (not my first one in series) ANDed with my Terminal Count coming from the first adder?