#### Joe24

Joined May 18, 2007
52
Hello all,

I will be working on a 16-bit Adder for school project and I have two questions regarding it:

1) Comparing a 16-bit Carry Ripple Adder using static CMOS compound gates with that of a 16-bit Carry Look Ahead Adder, is the speed increase in the CLA significantly greater or not by much?

2) Regarding the CLA, if use Pseudo-Nmos logic, I know that Pseudo Nmos logic is faster, but will it consume more power than a CLA designed with static CMOS logic? If so, is the increase in power consumption very high??

Thanks

#### Dave

Joined Nov 17, 2003
6,970
Hello all,

I will be working on a 16-bit Adder for school project and I have two questions regarding it:

1) Comparing a 16-bit Carry Ripple Adder using static CMOS compound gates with that of a 16-bit Carry Look Ahead Adder, is the speed increase in the CLA significantly greater or not by much?
The CLA is considerably faster than the CRA because by design of the lookahead circuitry the CLA has all the carry-bits available after the first clock - this is not the case for the CRA which must wait for the carry-bit to "ripple" from least to most significant bits. The more bits the slower the CRA - a restriction that does not inhibit the CLA.

2) Regarding the CLA, if use Pseudo-Nmos logic, I know that Pseudo Nmos logic is faster, but will it consume more power than a CLA designed with static CMOS logic? If so, is the increase in power consumption very high??

Thanks
The increase in consumption of power in pseudo-nMOS is due to a conduction path from Vdd to GND when the nMOS transistor is on, i.e. the output is low via ratioed-logic. When the output is high, the resistor pulls the output to Vdd and no current flows, hence the power dissipated is low (theoretically zero). So in a nut-shell pseudo-nMOS is faster because it derives only one gate input from the next stage (unlike static CMOS which drives two gates), however there is the penalty of higher power consumption because of the ratioed logic when the output is low.

Dave

#### Joe24

Joined May 18, 2007
52
Dave,

Is the Power consumption so high that it becomes a bad design idea? Or do you think that the speed up, in a way, compensates for this increase in power consumption?

Thanks

#### thingmaker3

Joined May 16, 2005
5,084
Trade-off between speed and power depends entirely on application. Example one: a circuit controlling a rapid-but-delicate factory process would need speed, and the designer would be willing to consume lots of power. Example two: a battery operated camping gizmo might only need to process once every few seconds, but need to run from the battery for days or weeks.

#### Dave

Joined Nov 17, 2003
6,970
Dave,

Is the Power consumption so high that it becomes a bad design idea? Or do you think that the speed up, in a way, compensates for this increase in power consumption?

Thanks
Given that, nowadays, CMOS is the de-facto and pseudo-nMOS is pretty much obsolete (primarily because of it's power consumption characteristics), I think that speaks volumes.

Why? Given the miniaturisation of MOSFETs (including for CMOS applications) the RC time constant is reducing, hence is becoming less of a factor in performance (RC ~ 2RC if C $$\rightarrow$$ 0); at the same time the power dissipation in CMOS applications is (practically) zero compared to a considerable level for pseudo-nMOS - this is relatively static.

Dave