cadence

  1. R

    gds file conversion from RTL

    I want to convert ISCAS benchmark's (for example c17 , c432) Verilog files to gds files (gate level to gds conversion). Also, I have to use the open-source standard cells NANGATE45. Is there any open source tool for gate-level to gds converter which can be done with NANGATE45?
  2. Alex_Khan

    Problem in Process corner simulation using Cadence ADXL tool.

    Hello, My question is related to CADENCE software simulation. I am doing a process corner simulation of a simple inverter using ADXL in CADENCE. But the problems are: 1_ When I run only the nominal corner it simulates successfully as shown in the figure. 2-But when I add worse power /worse...
  3. Alex_Khan

    MOSFET's model selection for different voltage source (Vdd).

    Hello, I have a question, please guide me and make me correct regarding MOSFET model selection? Although I used ‘nmos4’ both for 3.3V and 5V Vdd (supply voltage) in my simulation(cadence Virtuoso 6.1.6-64b), in both cases, it works fine and gives same results (according to my observation). So...
  4. R

    Calculation of Psat in cadence

    Hi, I am trying to figure out the Output saturation power of an amplifier for different frequencies of operation. I am using the PSS analysis in cadence and it only gives me 1dB compression point both input and output referred. Is there a way to find out Psat directly or from these values? I got...
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