Simple PEAK DETECTOR maxing out at 6 V

Hello,

I've built a simple peak detector circuit that is meant to output as DC the peak input voltage. It works just fine when the input stays below around 5–6 volts, but above that the output appears to saturate at roughly 6.4 V.

The actual input this circuit is expecting is a series of short positive pulses (~100µs @ 10 Hz), and there is potentially some DC drift at the input so I've added a high-pass stage. The input peak voltages can be set to anywhere from 100mV to 10 V, and the rail-to-rail voltage is 15–16 V (a 9V and 7660S chip*).

Again, everything is just fine for lower voltages, but my two questions are:

1) Why does the output saturate at 6 V for high input voltages?

2) Why is the output's rise time nice and fast for inputs of 3 V or less, but steadily slower and slower for higher input voltages?

I've attached an image of the circuit with some component specs and model numbers.

Thanks for reading, and any thoughts on this would be terrific!


(*when I tried it with just the 9V and no 7660, the same thing happened, just at a slightly lower voltage: ~5 V)

Your "output" is the voltage on the 100µF cap, right? That's going to be limited by the max output voltage of the op-amp (I don't think it goes to the rails) and by the 0.7V drop across the diode. [edit] Oops, just saw you're using a 15V supply. What's your reference voltage?

An answer for #2 hasn't dawned on me yet.

Rogare said:

2) Why is the output's rise time nice and fast for inputs of 3 V or less, but steadily slower and slower for higher input voltages?

Click to expand...

Because there is a slew rate limitation. The LM358 is pretty slow, you might try something faster like an LF356 and see if it slews faster.

There is also a charge rate limit on the capacitor. The op amp output can only source maybe 20 ma and the cap charges at the rate set by that.

No offense, I agree with your points, but do either of those points explain why it's slower at higher voltage? That's what's got me stumped.

Thanks for the replies.

wayneh: Yup, the output is on the 100 µF capacitor. This is probably a silly question on my part, but what do you mean by reference voltage?

bountyhunter: I'm not sure if this sheds any light on the slew rate issue, but I increased the frequency (duty cycle) of my pulses and there was no effect on that saturation voltage.

(Also, I'm not sure if this matters, but I use the same ground for the power supply and the input/output.)

Your op amp is saturating because the output can only go to within about 2V below the positive rail. With a 9V supply (fresh battery), your output is limited to about 7V. The diode reduces this to around 6.4V.
Use an op amp with MOSFET inputs. Then you can use a much smaller cap, because your cap won't be charged by the input current between pulses, or discharged by the leakage of a big electrolytic cap. Your cap will also charge much faster.
How do you discharge the cap to accommodate changes in peak voltage?

Rogare said:

This is probably a silly question on my part, but what do you mean by reference voltage?

Click to expand...

The voltage applied to the inverting input of the op-amp, the one that is not the signal.

And note Ron's point about discharging the cap. As drawn, that cap should hold a voltage for weeks. It's probably discharging slowly through your meter?

Hello,

The following PDF's from TI will give you a lot of information on the use of opamps:
sloa011Understanding Operational Amplifier Specifications.pdf
sloa058 A Single-Supply Op-Amp Circuit Collection.pdf
sboa092a_handbook_of_operational_amplifier_applica tions.pdf

On page 87 and 88 of the sbo092a, you will find info on precision rectifiers and peak detectors.

Bertus

Hi Ron, my rail goes from 0 up to about 15 V, so I think I'm OK on that front? Re: discharging, it isn't on the diagram but I'm going to have a "reset" button that shorts the capacitor to ground (maybe over a small resistor). (Yes, it's very slow to discharge, but using a lower capacitance means that I lose too much voltage between input pulses.)

Just to clarify, does "an op-amp with MOSFET inputs," mean a type of op-amp or an op-amp configuration?

wayneh: The reference voltage then would be the same as the output voltage; I haven't wired anything else to it.

Rogare said:

wayneh: The reference voltage then would be the same as the output voltage; I haven't wired anything else to it.

Click to expand...

Got it. I didn't realize there was a connection there, I thought the wires just crossed.

If you really have 10V peaks coming in, I can only speculate that 1) the source has a high impedance, so that the op-amp and 500k resistor together bring down that peak or 2) the peaks to 10V are too few and too brief for the op-amp to equilibrate the capacitor.

My money is on #2. Testing a faster amp would help rule it out.

The slew rate of a lousy old LM358 is so slow that it has trouble above only 2kHz.
Half a cycle of 2kHz is 500us. For a fairly fast risetime then 50us is needed. But your pulses are 1/5th as long.
Use a faster opamp.

Do you want your cap to fully charge within the 100us pulse width? With a 100uF cap, you voltage will rise by around 20mV with each successive pulse. With a 10V pulse, it will take about a minute for your cap to reach 10V. Is that OK?
If not, you need a MUCH smaller cap. This is why I recommended a CMOS op amp (I originally said an op amp with MOSFET inputs - pretty much the same thing). You won't be able to monitor the cap with a scope probe, because it will discharge the cap between pulses. You will need a voltage follower. A dual CMOS op amp will do all this nicely.
If you want design help, ask for it here.

Thanks everyone for the replies!

wayneh: I've measured the signal right at the op-amp non-inverting input (after the filter stage), and it has the same peak-to-peak voltage as the input, so I think that answers question 1. I'd be happy to try a faster op-amp; presumably this means one with a faster slew rate? Maybe a TL072? (If there's an industry standard for fast, cheap op-amps, please share! I've put a list of what I have access to at the bottom of the page, in case any model number rings a bell.)

Ron: It's OK if it takes a few pulses. Everything actually works great up until the input pulses get to about 5 or 6 V. It takes maybe a second (max) to get up to 5 or 6 V, but that's about where it slows and slows and then finally stops. It just seems so strange that everything works for inputs below 5 V, but the system saturates above 6 V; I'm kind of keen to figure this one out before moving to a new design, but I appreciate the pointer of what to try next!


Available op-amps:
TL061, TL062, TL064, TL071, TL072, TL074, TL081, TL082, TL084, LM301A, LM311, LM318, LM319, LT319, LM324AN, LM339, LM348, LM358, TEA2025B, LM386-4, LM393, LF411, LM833, uA741, MC1458, TEA2025B, CA3140A, MC33172, RC4558, MCP6002, MCP6004, LM358

The LM318 is the fastest opamp you have. But it is so fast that it will probably oscillate at a high frequency if you build the circuit on a breadboard. Use a pcb.

Like most opamps, it will need a positive and negative supply.

Ron H said:

This is why I recommended a CMOS op amp (I originally said an op amp with MOSFET inputs - pretty much the same thing). You won't be able to monitor the cap with a scope probe, because it will discharge the cap between pulses. You will need a voltage follower. A dual CMOS op amp will do all this nicely. If you want design help, ask for it here.

Click to expand...

Ron, could you recommend a particular dual CMOS op amp to try? I've been looking through datasheets, but was there one in particular you tend to use? (My possibilities are a bit limited—I put them in a post above.)

Here is a circuit for a positive peak detector I have used many times. You could substitute a FET op-amp like LF-356. U2-B acts as a buffer so the voltage on the peak capacitor isn't drained off quickly. Using a smaller cap lets the circuit ramp up faster.

bountyhunter said:

Here is a circuit for a positive peak detector I have used many times. You could substitute a FET op-amp like LF-356. U2-B acts as a buffer so the voltage on the peak capacitor isn't drained off quickly. Using a smaller cap lets the circuit ramp up faster.

Click to expand...

I was simulating a very similar circuit when you posted this. You will get less overshoot on the peak held value if you move the input to the voltage follower to the other side of the resistor, as in the attachment.
With the values shown, a 10V, 100uS wide flat-topped pulse can be fully acquired in one pulse. A larger R5*C1 will result in requiring more than one pulse for full acquisition. Droop in the sim was primarily due to leakage current through D1. With the values shown, simulated droop was about 2.6mV per 100mS. In hardware, the results will be different. A larger value of C1 will reduce droop, as will a low leakage diode, like BS116.
This works in simulation with either LM356 or CA3140.

EDIT: I noticed a strange quirk in LTspice. As shown, the sim runs pretty fast. If I change the diodes to 1N4148 (model is identical to 1N914), the sim still runs fast. If I make D1=1N914 and D2=1N4148, the sim starts veeerrry slowly. I didn't have the patience to see if it sped up later on.

Rogare, how did you have your power supplies connected? I assumed it was something like one of the block diagrams in the attachment.
Which way was it - or did you have some other power supply scheme?

Ron H said:

I was simulating a very similar circuit when you posted this. You will get less overshoot on the peak held value if you move the input to the voltage follower to the other side of the resistor, as in the attachment.

Click to expand...

I think your sim is lying to you. There is a voltage drop across that resistor caused by the current to charge the cap up. So taking the tap to feed the input of the buffer op amp there will give a false high voltage while the op amp is charging the cap. I don't think that will help, I think it screws it up. The voltage at the cathode of D1 can significantly exceed the final voltage on the cap during the transition, so the output of the buffer will actually "overshoot" worse.

Ron H said:

Rogare, how did you have your power supplies connected? I assumed it was something like one of the block diagrams in the attachment.
Which way was it - or did you have some other power supply scheme?

Click to expand...

Hi Ron, I believe it was the second configuration. And thanks for spending the time simulating this circuit, much appreciated!