Full adder ladder logic correction

This diagram is given as ladder logic for full adder in the section Volume IV - Digital » COMBINATIONAL LOGIC FUNCTIONS » Full Adder.

The last rung should be C1 and C2 in parallel to form an OR gate instead of series connection given.

You are right. Thanks for the correction!

manulal said:

This diagram is given as ladder logic for full adder in the section Volume IV - Digital » COMBINATIONAL LOGIC FUNCTIONS » Full Adder.

The last rung should be C1 and C2 in parallel to form an OR gate instead of series connection given.

Click to expand...

Thanks manulal for pointing us to this error.

I have changed the image to include OR gate in place of AND gate
Old image: http://forum.allaboutcircuits.com/image_cache/httpsub.allaboutcircuits.comimages04477.png
New image: http://openbookproject.net/electricCircuits/Digital/04477.png

These other images needed the same change 04478.png:
Old image: http://sub.allaboutcircuits.com/images/04478.png
New image: http://openbookproject.net/electricCircuits/Digital/04478.png

And finally this image 04479.png:
Old image :http://sub.allaboutcircuits.com/images/04479.png
New image: http://openbookproject.net/electricCircuits/Digital/04479.png

The images have been updated at ibiblio.org (They host openbookproject.net on their servers)