In this design, I am traversing away from the classical method of building the BCD counter, where traditionally the flip flops are synchroneously clocked, in my design I'm synchroneously applying clock pulses to an array of logic gates at the decoder circuitry instead.
With this design it can lend itself to programmable outputs, where the count sequence can start and end any where as well as the counts can jump from any number to the next depending on how it is programmed.
However I don't demonstrate that feature, because that would require a diode and wire connection from every output of the decoder, to the SCR inverter, of every other decoder gate array, in order to remove the latching signal of the previous latching output, to cause the output to remain low during subsequent clock inputs.
The method of removing the latching signal via inversion input to an SCR, is described in the video, as I explain the way the previous output of the decoder needs to be shut off to allow a new output to show.
This and more coming up. enjoy.
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