Hi fellas
This is my the PCB I've drawn:

I shared it here to know if you think any-part of it has any problem. I would appreciate any suggestion.

U3 is AMS1117 3v3 LDO. my MCU(U1) is an STM32f103. the LDO should supply the MCU and the back-light of a 2.2" TFT LCD. not sure if the LDO could handle this. the input of the LDO is 5v 3A.

Q2 is an IRF9530 and is supposed to switch a rectified 25-30V 3.5A AC. can a MOSFET switch an rectified AC current? are we allowed?
can its traces which I've drawn handle 3.5-4A AC?

 

Hard to guess the size of a trace from a little jpeg
If you measure the width of the trace and the thickness of the copper you can determine the cross-section area of the conductor.
That determines current limits for a PCB trace. Google it and you'll get thousands of hits for charts and things that will tell you what the power handling limit is for any trace size.
If you have questions about your circuit operation, you need to post your schematic.

 

From first glance this is some very nice work.
But I have a few questions:
What is the highest frequency on this board and where?
Any analogue signals?
Digital signals?
Numbre of layers?

 

What is the highest frequency on this board and where?
Any analogue signals?
Digital signals?
Numbre of layers?

I'm controlling my LCD over a 36MHz SPI interface.
alone analogue signal is just a rectified 25-30v 50Hz AC.
The board is two layer.
I'm thinking to define "Polygon Pour" on both layers using "Polygon Pours" .

 

You might want to adjust some of your silk screen text so that the reference designators are located better in relation to the components, and so none will be hidden under components or on top of vias.

 

If your board is only two layers, why are there three colors of traces (red, blue and green)? Also, your PCB package doesn't allow traces on the bottom to show even if a trace on the top covers it. Your bottom traces will just disappear under the top traces.

 

You might want to adjust some of your silk screen text so that the reference designators are located better in relation to the components, and so none will be hidden under components or on top of vias.

Thanks but ignore "adjusting silk screen text". let's just talk about the technical stuff. e.g. should I fill the free(empty)space of the board with "Polygon Pour"?

If your board is only two layers, why are there three colors of traces (red, blue and green)? Also, your PCB package doesn't allow traces on the bottom to show even if a trace on the top covers it. Your bottom traces will just disappear under the top traces.

ignore the green traces. that's because of overlapping the pads of a resistor on two traces. I did it on purpose but you ignore it.

 

............ should I fill the free(empty)space of the board with "Polygon Pour"?...............

Yes. Since you do not have a ground plane I highly suggest that you pour it on at least one side. Be cautious of isolated planes, remove them.

 

I'm controlling my LCD over a 36MHz SPI interface

Did you really meant that ? I have to admit that I'm somewhat outdated with the newest technologies, but for such a high transfer rate I would consider routing of the communication bus with a matched impedance approach.

 

A schematic would be helpful. I guess the gray traces are the SPI? Could you provide some more detail on that, and a datasheet of the LCD display?

Also, does the board need to be so huge? You could easily do it in a third of the length if you used smd resistors and capacitors and played a little with the layout. Since this is a two layer board, due to its thickness I doubt a ground plane would get you controlled impedances that would fit, but still having the botom as solid ground plane as possible will definitely give you better results.

 

When you say Q2 is switching rectified AC, I'm assuming that means that the drain will always have a voltage more negative than the source for this P-channel transistor. If the drain ever goes more positive than the source, there is a diode inside Q2 that will conduct, even if the transistor is "off".

If Q2 will be carrying 3.5 A, and Rds(on) is 0.3 ohms, that's about a watt of dissipation when the transistor is on. But that's only half the story. If the transistor turns on slowly, or is weakly driven, or is switched at a high frequency, power dissipation will be more. You may want to leave space for a heat sink if you have not breadboarded the circuit.

Also, if I'm reading right, I see Q2 drain going to P5, and changes layers (goes through a via). A via is good for a couple amps, usually, but I'd avoid it if possible. In this case, you could route the path entirely in blue. You could still have a via if you want to bring out a test point to the other side of the board, just don't count on the via being the main current path.

Consider some copper pour area as a heatsink for U3.

Do you need any mounting holes on the board? Or if the board will be held in a plastic slide, is there enough edge clearance to accommodate the slide?

Do you need any test points? Since you have mostly through-hole parts, this is less necessary, as you could clip onto component leads. I like to have at least one extra hole dedicated as a place where I can attach the ground of my meter or oscilloscope. If there is any signal on that fine-pitch QFP U1 that does not already come out to an easy place to probe, and you might want to monitor that signal, bring it out to a test point.

 

Yes. Since you do not have a ground plane I highly suggest that you pour it on at least one side. Be cautious of isolated planes, remove them.

Ok. isolated planes? what do you mean "isolated planes"? what is it?

Did you really meant that ? I have to admit that I'm somewhat outdated with the newest technologies, but for such a high transfer rate I would consider routing of the communication bus with a matched impedance approach.

Yup! I assembled this LCD on breadboard and connected it to the MCU with breadboard wires and it worked perfectly. alone problem that I had was "timing". I figured it out just by changing the timing.

A schematic would be helpful. I guess the gray traces are the SPI? Could you provide some more detail on that, and a datasheet of the LCD display?

Yes, those gray traces are the SPI lines. I tuned them. this is my LCD:

https://www.adafruit.com/product/1480

Also, does the board need to be so huge? You could easily do it in a third of the length if you used smd resistors and capacitors and played a little with the layout. Since this is a two layer board, due to its thickness I doubt a ground plane would get you controlled impedances that would fit, but still having the bottom as solid ground plane as possible will definitely give you better results.

Yes. I guess I will not have any problem. nonetheless I going to pure both side of the board.

When you say Q2 is switching rectified AC, I'm assuming that means that the drain will always have a voltage more negative than the source for this P-channel transistor. If the drain ever goes more positive than the source, there is a diode inside Q2 that will conduct, even if the transistor is "off".

If Q2 will be carrying 3.5 A, and Rds(on) is 0.3 ohms, that's about a watt of dissipation when the transistor is on. But that's only half the story. If the transistor turns on slowly, or is weakly driven, or is switched at a high frequency, power dissipation will be more. You may want to leave space for a heat sink if you have not breadboarded the circuit.

Also, if I'm reading right, I see Q2 drain going to P5, and changes layers (goes through a via). A via is good for a couple amps, usually, but I'd avoid it if possible. In this case, you could route the path entirely in blue. You could still have a via if you want to bring out a test point to the other side of the board, just don't count on the via being the main current path.

Consider some copper pour area as a heatsink for U3.

Do you need any mounting holes on the board? Or if the board will be held in a plastic slide, is there enough edge clearance to accommodate the slide?

Do you need any test points? Since you have mostly through-hole parts, this is less necessary, as you could clip onto component leads. I like to have at least one extra hole dedicated as a place where I can attach the ground of my meter or oscilloscope. If there is any signal on that fine-pitch QFP U1 that does not already come out to an easy place to probe, and you might want to monitor that signal, bring it out to a test point.

Thanks. good points. this is the schematic of the MOSFET:

 

An isolated plane is where a part of the poured ground plane is "cut off" from the rest of the ground plane by other traces. It does you no good and can enhance parasitic coupling.

 

An isolated plane is where a part of the poured ground plane is "cut off" from the rest of the ground plane by other traces. It does you no good and can enhance parasitic coupling.

Thanks
How about to connect them to the ground instead of removing them?

 

Does a small piece like this make any difference? At 30 mhz I don't think.

Also these TFT displays don't see spi signals with 36 mhz clock. They'll drop off much before of that

 

Does a small piece like this make any difference? At 30 mhz I don't think.....

It is a poor practice to leave isolated planes on a PCB design no matter the frequency.

 

It is a poor practice to leave isolated planes on a PCB design no matter the frequency.

For aesthetic reasons? Agree. But if you put a legend or labels as copper? Its many small isolated traces. Looks better than silkscreen.

OP could eliminate some parts for the MOSFET drive. It only needs one resistor and one n-channel mosfet to ground it.

The Z diode is not required as well 1K for gate bias is quite low.
Its a heater you could put 1M Ohms. Low value is only used for very fast switching.

If the LDO can handle 3 Amps then it will be fine with a MCU and a small display.

Whats the point of heating off one watt with the MOSFET?
You could ground the gate with the MCU if the gate bias resistor is high enough (which you can afford since its a slow heater).
If it has open collector outputs.

Probably most of the components could be eliminated.

 

It is a poor practice to leave isolated planes on a PCB design no matter the frequency.

For aesthetic reasons? Agree. But if you put a legend or labels as copper? Its many small isolated traces. Looks better than silkscreen.

No, as mentioned above, isolated planes enhance parasitic coupling, effectively acting as scattered series capacitors which even having a small effective value, for EMI with higher frequencies is worse than having no metalic plane. If he wants to keep the plane there, could think about somehow route the ground to there by using vias.

 

No, as mentioned above, isolated planes enhance parasitic coupling, effectively acting as scattered series capacitors which even having a small effective value, for EMI with higher frequencies is worse than having no metalic plane. If he wants to keep the plane there, could think about somehow route the ground to there by using vias.

Well I see they could act as small capacitor close to traces. This wouldnt be of much concern for labels as they usually are thin isolated lines.

What frequency would you say would start to see effects from that?

OP has signals with probably a few MHz but these are digital.

 

What frequency would you say would start to see effects from that?

OP has signals with probably a few MHz but these are digital.

I don't think we could state digital 36MHz signals as "Few MHz signals".
It is within and even above of the bandwidth range of most RF telecommunication systems.

Keep in mind that a squared waveform digital signal has not only its findamental frequency of 36MHz, but also a lot of components of odd multiple frequencies, being the 3rd harmonic 108MHz the most relevant.