There is a way to make it work with v4, but v3 is fine. I'd say forget v4

I've look at the datasheet for your 4024 and 4082 in v3. The sum of propagation delays in the "reset loop" (reset counter -> and-Gate goes low -> reset goes low again) is good enough to make a pulse that is satisfying to the reset and clock inputs.

If you wanted to increase the margin to the required minimum pulsewidth on the reset input, you could add some "piff" to the reset input (putting a pico Farads sized capacitor back into the circuit as before) to add some more delay. You may ask why we put a capacitor back in to the circuit when it made things worse the last time, well the cap that was used in v2 (?) was in the size of nano Farads, and it basically filtered out the shape of the pulse from the AND-gate into the shape of a shark fin, not even reaching full VDD for the reset input. This time it would be just a slight slowing down of the rise time to make the delay longer. I checked the 4024's datasheet for capacitance that is allready present on the input pins, and it is about 5-7pF pr input.. Thats 10-14pF for both reset and clock connected together. Connecting a 22pF cap would triple the capacitive load making it slightly slower, and not as bad as adding the 100nF as before (who is in order of 10000 times larger). You could experiment with this, but its best to have an oscilloscope to see what the signals look like when doing this.

I'm sorry if my previous post is confusing. I'm not good with language and grammars, not even in my own native language. I'll try harder.

 

Ok, here's a question for you...and I think it involves a capacitor or three...but I'm not sure. Think about regular digital clocks and their set buttons.

When you press the button once, it sends a single pulse to the clock to increment it by one...When you press the button and hold it for a second, it increments it by one, then pauses for a brief second and starts incrementing a little faster. (like the 4 and 8 hz setting buttons I have now).

How can I achieve an effect such as this? Currently, a single press of the button requires a clock pulse to happen to be passing through the circuit during the press and release of the button. This means theoretically (and I've proven this theory) that I can quickly press the button and release it between a clock pulse and get no effect. This occurs when I'm getting close to the number I want to reach, and I press and release fast to try and get a single increment.

What can I do so that when the button gets pressed, the signal goes high for a brief moment, then reverts to 4hz (or 8hz depending) clock pulses?

 

I understand, that sounds like a typical scenario for adjusting a digital clock

What you want when the button is _held_ is basically is to:
1. increment a counter when you click the button disregarding the CLK signal (use the word asyncronous when you want something to happen undependent of the CLK ),
2. make a pause,
3. then speed up the clock.

A pause you can get from a monostable flip-flop, or a one-shot circuit (typical 555, or logic gates, or even lm339 Quad comparators!. I'm thinking you need some multiplexing. Somehow you need to combine the output of the one-shot with the button and 4hz signal. Drawing the signals will help you figure out the logic gate configurations you would need. I'll make a quick mashup but I can't say if it will work (its very late), or it may need optimization and button debouncing... Hmm unsure where to put the 1Hz signal, maybe like before? I mean like the button attached to the 1Hz signal via resistor?...

I'll look more at it tomorrow.

Maybe you are right, maybe there is a simpler way with capacitor for delay, and some logic gates to mix in the 4Hz signal after a while, but how would you get the first pulse ?

 

What about using a 4024 for the delay, and simple edge detect circuit for the initial async pulse ?

See my drawings where I suggest one 4024 counter and logics optimized to one Quad NAND package. SgtWookie was in on sticking to CMOS circuits in the biginning of the thread, this is good if you wan't the circuit's running at low power.

I may have swapped plases betwenn R1 and SW, SW should be connected to ground(VSS) and R1 connected to VDD.
Opps looks like I screwed up the left side of the boolean equations. should say "OUT =" at the left side.

edit: I'm just testing TeX here:

\(OUT = 4Hz \cdot Q_3 + SW \cdot \overline{SW}
OUT = \overline{\overline{4Hz \cdot Q_3 + SW \cdot \overline{SW}}}
OUT = \overline{\left(\overline{4Hz \cdot Q_3}\right) \cdot \left(\overline{ SW \cdot \overline{SW}}\right)}
\overline{OUT} = \overline{4Hz \cdot Q_3} \cdot \overline{ SW \cdot \overline{SW}}
\)

 

Wow, that's pretty confusing stuff. Maybe I should just put what I have (v3.0) to PCB and make that a separate project. I don't want to add too many IC's to my project because my project box is already pretty small. If there were a way to get single gates, that'd be cool...Is there?

 

That would be one counter package + one nand package for the pulse->delay->4Hz function, followed another NAND package to multiplex this signal to hours, minutes and seconds. The buttons would then have to be double pole, where one of the poles are parallell with all buttons to set off the delay, and the other pole to hours, minutes or seconds (on the input of the nand gate).

Yeah, v3 is way more sufficient than doing all this just for convinience

With a mcu you would do all (!) in a single package, and you can also get nanowatt devices too. Currently you are in the microwatts with this design, where the sacrifice of the last nand gate blasted the current pull up a notch. Do you wan't to have a backup battery ? I'm interested to see how such would be designed into this..

 

I'd love to have a backup battery for this, I just don't know exactly where to begin. It would involve making the leds not light when external power isn't on.

 

You need isolation between the 9V, battery and the LEDs. I'm not sure if a 3V minus the voltage over the diode will be able to power the logic circuits..

Here is my suggestion, note the changes at the power input at the top left of the schematics, and the NMOS transistor providing control over the diodes wheter or not the 9V is present, if the 9V is not present, the pulldown resistor at the NMOS ensures it beeing off. The diode on the battery protects its from being charged, and the diode on the 9V input protects the battery from discharing through the powersupply incase the powersupply is loosing AC-power.