Xilinx Map Error: IDEALYCTRL

Discussion in 'Embedded Systems and Microcontrollers' started by Brownout, Feb 14, 2013.

  1. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    I'm using ISE V14.4 and Xilinx Platform Studio (XPS) to generate a system with multiple axi-ethernet cores in Kintex-7 Techonolgy.
    My method was to use Base System Builder to instantiate one axi-ethernet core, then instantiat a second one from the IP Catalog. Mapping failed witht the following message:
     
    MapLib:1002 - IDELAYCTRL processing failed. IDELAYCTRL symbol "system_i/ETHERNET/ETHERNET/SOFT_SYS.I_TEMAC/GEN_GMII.I_GMII/GEN_V6.dlyctrl" (output signal=<none>) and IDELAYCTRL symbol "system_i/axi_ethernet_0/axi_ethernet_0/SOFT_SYS.I_TEMAC/GEN_GMII.I_GMII/GEN_V6.dlyctrl" (output signal=<none>) have the same IODELAY_GROUP constraint but do not share the same Reset signal.


    Here is the .ufc file generated from XPS:


    ############################################################
    # GMII: IODELAY Constraints
    ############################################################
    # Please modify the value of the IDELAY_VALUE
    # according to your design.
    # For more information on IDELAYCTRL and IODELAY, please
    # refer to the Series-7 User Guide.
    INST "*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 30;
    INST "*gmii_interface*delay_gmii_rx_er" IDELAY_VALUE = 30;
    INST "*gmii_interface*delay_gmii_rxd" IDELAY_VALUE = 30;
    # Group IODELAY and IDELAYCTRL components to aid placement
    INST "*gmii_interface*delay_gmii_rx_dv" IODELAY_GROUP = "grp1";
    INST "*gmii_interface*delay_gmii_rx_er" IODELAY_GROUP = "grp1";
    INST "*gmii_interface*delay_gmii_rxd" IODELAY_GROUP = "grp1";
    INST "*dlyctrl" IODELAY_GROUP = "grp1";
    OFFSET = IN 2.4 ns VALID 2.8 ns BEFORE "ETHERNET_RX_CLK";

    Shows wildcard being used to apply dealy group names to all instances of the dealy components, so those group constranits will be applied across every instance of ethernet. This obviously causes the error.

    The constraints guide says this about IODELAY_GROUP:


    Groups a set of IDELAY and IODELAY constraints with an IDELAYCTRL to enable
    automatic replication and placement of IDELAYCTRL in a design.

    Not sure what the rules of replication are. Also not sure if they apply here, because these IDELAYCTRL components are instantiated within the design, and not inserted by the software. So, is the IODELAY_GROUP relevant in this design?
    In Xilinx support answers 38440 here: http://www.xilinx.com/support/answers/38440.htm
    It states that (for this same issue but caused by DDR3 controllers) each core should have a different IODELAY_GROUP set. However, in the Xilinx forum here: http://forums.xilinx.com/t5/Implementation/erro-maplib-1120/td-p/102220, a Xilinx employee states that when multiple IDELAYCTRL components are in the design, you must use LOC constraints for each IDELAYCTRL, or else build a single group and the placer will replicate as needed. Again, no idea of what it means to be replicated, nor when I can expect that to happen.

    Further, I would like to either use LOC constraints on the instances of IDELAYCTRL or define unique groups (whichever actually works) but as the axi-ethernet core is a xilinx deisgn, I don't have any information as to the instantiations. I try to push down to the IDEALYCTRL instantiaitons in RTL view or Technology view, but cannot push into the XPS generated system. Niether can I see the instances window to see the heirarchy. Further, the error message shows a hierarchy to the componenets that does not contain in instance of "gmii_interface" as shown in the .ucf file.

    So finally my questions. What constraint do I need to successfully map this design. How do I find the hierarchy path to the components that I need to constrain? When can I expect the software to "replicate" the IDELAYCTRL comonent as needed? And what exactly does that mean? And finally, how can I push down into a XPS system from the ISE software?
     
     
  2. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    Sorry about the weird fonts. I pasted this from my Word document. It didn't like like this.
     
  3. t06afre

    AAC Fanatic!

    May 11, 2009
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    As a hint. This button remove text formating. Leftmost on the message toolbar [​IMG]
     
  4. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Are you familiar with the generate command?

    Muliple Cores Design Document is for small processing cores, which your net IPs are. There might be something in there missed.

    System builder doesn't always get things perfect.
     
  5. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    Im using Platform Studio so that I don't have to figure out how to connect the cores. It generates the whole system, including the interconnects. There is obviously a problem though. I'm going to open a case on their support site.
     
  6. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    Sorry I can't assist more in this area. I'm assuming you are getting that error in testbench sim, prior to synthesis?
     
  7. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    It's OK. I'm throwing this out on many forums, including Xilinx forums and see what comes back. Actually, my collegue and I came up with a possible solution. I might be able to set a unique delay group constraint for each ethernet core, and use the constraints syntex from above, for example:

    INST "*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 30;


    Only prefix each hierachy path with the core name, for example:

    INST "*ethernet0*gmii_interface*...

    where "ethernet0 is the name of the core. That way, I can define a unique group for each "ethernet0" "ethernet1" etc. That simple idea alluded me during the comotion of trying to track down the root of the problem.

    This is clearly a xilinx tools snafu. This crap will make you old before your time.

    I'll post the results after testing...
     
  8. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    BTW,

    It's an error in Map. I'm not at the point of simulation yet. I'm just quickly building a rough design to get an estimate of resource usage.

    I don't care if it works yet :)
     
  9. Brownout

    Thread Starter Well-Known Member

    Jan 10, 2012
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    Yea! It works! Here is what I changed from the above constraints:

    INST "*ETHERNET*gmii_interface*delay_gmii_rx_dv" IDELAY_VALUE = 30;
    INST "*ETHERNET*gmii_interface*delay_gmii_rx_er" IDELAY_VALUE = 30;
    INST "*ETHERNET*gmii_interface*delay_gmii_rxd" IDELAY_VALUE = 30;
    # Group IODELAY and IDELAYCTRL components to aid placement
    INST "*ETHERNET*gmii_interface*delay_gmii_rx_dv" IODELAY_GROUP = "grp1";
    INST "*ETHERNET*gmii_interface*delay_gmii_rx_er" IODELAY_GROUP = "grp1";
    INST "*ETHERNET*gmii_interface*delay_gmii_rxd" IODELAY_GROUP = "grp1";
    INST "*ETHERNET*dlyctrl" IODELAY_GROUP = "grp1";


    The entry "ETHERNET" in the path name to the delay controls is the name of one of the ethernet instantiations. By rule, you can leave one group unconstrained, so I don't have constraints entered for the other core. If I had a 3rd core, I'd need to have two set of constraints.
     
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