xilinx ise map report

Discussion in 'Homework Help' started by virgo1900, Mar 18, 2012.

  1. virgo1900

    Thread Starter New Member

    Sep 9, 2011

    I ve been trying to sythesize a design of my circuit in xilinx ise. i coded the design in verilog.

    The simulations work fine. The problem is this-

    When I look at the gate count using the BELS feature in the map report..the number of gates are different frm what i got on manually counting them.

    why is this so? Im guessing it has something to do with the LUTs.

    But i didn't use any behavioral logic (ie, no if constructs, switch case, loops) so extra gates could not have been added

    i practically almost defined each gate and explicitly defined each function..

    so why am i getting this huge difference in the number of gates?

    is there any way i can have the equal number of gates in the report as well as in my circuit ?

    the rtl schematic also looks a bit weird..i didnt even use some of the gates (like there was a 3 input AND in the report but for which there was no mention or need of in my code).. someone help me out please.
  2. guitarguy12387

    Active Member

    Apr 10, 2008

    You will want to post your .mrp and your code to get the most accurate assessment of what's going on... but have a look here:


    What device are you targeting? I ask because 6-series and later devices use a 6-input LUT and previous architectures use 4-input LUTs.

    I suspect that the reason for the discrepancy is that the tools are handling the circuit in a way you aren't expecting them to. For example, if you have a 10 input and gate (slight exaggeration), it will use a bunch of LUTs to build that... not just one gate. Or, to go the other direction, the tools will infer ternary adders in 6-series or later devices. Thus you could get three-input adders with a single LUT.

    This suggests to me that you're not coding in a way that the tools would understand. Have a look at the XST users guide for info.