Xilinx ISE 14.7 - creating test bench with custom function file

Hey,

i am working on project in Xilinx ISE 14.7. For the purpose of the project i generate file with custom functions and type.
The new type which is declared in the file is used in port map.

Definition of type:
Type muxnto1_bus_type is array (natural range <>, natural range <>) of STD_LOGIC;

the file is imported with:
USE work.reg_file_functions.all;

the entity is

ENTITY muxnto1_bus IS

generic( n_addr : INTEGER := 2;
bus_width : INTEGER := 8 );
PORT ( s : IN std_logic_vector( n_addr - 1 downto 0);
w : IN muxnto1_bus_type( 2**n_addr - 1 DOWNTO 0, bus_width - 1 DOWNTO 0);
f : OUT std_logic_vector( bus_width - 1 downto 0)
);
END muxnto1_bus;

The problem is that when i want to create test bench, the xilinx ise generate only an test bench template.
I think that the source of the problem is custom type, used in port map.