Hi can any 1 please help me how to write the verilog code for some signals like CLK, CKE, RESET.
Iam attatching you the related files as well as my code. please check it out and help me.

`timescale 1ns / 1ps

module DDR3_Rst(
                  clk,
              Reset,
    cke
    );
     
     input clk;
     output Reset;
     output cke;
     
     reg Reset_i;
     reg cke_i;
     
 always@(clk)
 begin

 if(clk)
 begin
#0 Reset_i <= 1'b0;
#44 cke_i <= 1'b1;
 end
 
 else
 
 if(!clk)
 begin
#200655 Reset_i <= 1'b1;
  #189985 cke_i <= 1'b0;
#310162 cke_i <= 1'b1;
 end
 
 end
 
 assign Reset = Reset_i;
 assign cke = cke_i;
 
endmodule

 

Are you talking about test signals?

For clk:
parameter per=10;


reg clk;
....
initial begin
clk = 1'b1;
forever #per/2 clk = ~clk;
end

For reset
reg reset;

initial
begin
reset = 1'b0;
#100
reset = 1'b1;
end

etc.


Put these statements in your testbench file. The testbench should instantiate your design file, and these signals connect throught the instantiation port.