writing a verilog code for some signals

Discussion in 'General Electronics Chat' started by ideas, May 16, 2012.

  1. ideas

    Thread Starter New Member

    Mar 16, 2012
    7
    0
    Hi can any 1 please help me how to write the verilog code for some signals like CLK, CKE, RESET.
    Iam attatching you the related files as well as my code. please check it out and help me.
    Code ( (Unknown Language)):
    1.  
    2. `timescale 1ns / 1ps
    3.  
    4. module DDR3_Rst(
    5.                   clk,
    6.               Reset,
    7.     cke
    8.     );
    9.      
    10.      input clk;
    11.      output Reset;
    12.      output cke;
    13.      
    14.      reg Reset_i;
    15.      reg cke_i;
    16.      
    17.  always@(clk)
    18.  begin
    19.  
    20.  if(clk)
    21.  begin
    22. #0 Reset_i <= 1'b0;
    23. #44 cke_i <= 1'b1;
    24.  end
    25.  
    26.  else
    27.  
    28.  if(!clk)
    29.  begin
    30. #200655 Reset_i <= 1'b1;
    31.   #189985 cke_i <= 1'b0;
    32. #310162 cke_i <= 1'b1;
    33.  end
    34.  
    35.  end
    36.  
    37.  assign Reset = Reset_i;
    38.  assign cke = cke_i;
    39.  
    40. endmodule
    41.  
    42.  
     
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    Are you talking about test signals?

    For clk:
    parameter per=10;


    reg clk;
    ....
    initial begin
    clk = 1'b1;
    forever #per/2 clk = ~clk;
    end

    For reset
    reg reset;

    initial
    begin
    reset = 1'b0;
    #100
    reset = 1'b1;
    end

    etc.


    Put these statements in your testbench file. The testbench should instantiate your design file, and these signals connect throught the instantiation port.
     
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