write cycle of eeprom

Discussion in 'General Electronics Chat' started by bug13, May 3, 2015.

  1. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
    1,208
    38
    Hi guys

    I am looking at different eeprom, say this one for example:
    http://www.atmel.com/Images/Atmel-8819-SEEPROM-AT24C01C-02C-04C-08C-Auto-Datasheet.pdf
    It say 1M write cycle @ 25 degree C, that's pretty good.

    But what is 1 write cycle?

    Code A:
    Code (Text):
    1. eeprom_write_one_byte();
    Code B:
    Code (Text):
    1. eeprom_write_one_page();
    Code C:
    Code (Text):
    1. for (uint8_t i = 0; i < 128; i++)
    2. {
    3.     eeprom_write_one_byte();
    4. }
    Code D:
    Code (Text):
    1. for (uint8_t i = 0; i < 128; i++)
    2. {
    3.     eeprom_write_one_page();
    4. }
    etc...
     
  2. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    7,386
    1,605
    Each location is rated for those cycles, no matter if you write to it individually or as part of a group.
     
    bug13 likes this.
  3. AnalogKid

    Distinguished Member

    Aug 1, 2013
    4,516
    1,246
    A write cycle is the change in value of one bit, and this spec applies per bit. If you overwrite one bit 1 million times, but don't use some other bit at all, the first one will be running out of life and the other one will be as fresh as the day it was manufactures. This is why some flash memory devices and systems have what is called "load sharing". You think you are writing to the same location each time, but the system moves it around in memory to other unused locations so a small group does not get overused and shorten the long term reliability of the device.

    ak
     
    bug13 likes this.
  4. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
    1,208
    38
    Hi guys

    Just a couple more question regarding eeprom read/write cycle.
    • I don't see an eeprom datasheet states it's read cycle, and I read somewhere eeprom has unlimited read cycle, is that true?
    • In this 1G NAND eeprom here, it doesn't mention any erase/write cycle at all, what is the normally expect write cycle for these memory? I am under the impression that these type of memory use different mechanism to deal with write cycle, if that's the case, what is it?
    Thanks a lot guys!
     
  5. dl324

    Distinguished Member

    Mar 30, 2015
    3,235
    619
    Yes
    All NAND FLASH have array defects and you must use error correction to insure data integrity. Wearout is spec'ed differently for NAND than other nonvolatile memory. All other nonvolatile memory is considered worn out at first bit failure.
    All FLASH use Fowler-Nordheim tunneling for write and erase.
     
    Last edited: May 9, 2015
    bug13 likes this.
  6. RichardO

    Well-Known Member

    May 4, 2013
    1,230
    382
    It does not answer your question but page 41 of the data sheet addresses how the device fails.

    I agree that the data sheet is odd in that it does not give any numbers for life/failure rate.
     
    bug13 likes this.
  7. nsaspook

    AAC Fanatic!

    Aug 27, 2009
    2,907
    2,163
    It's pretty cool stuff how the 'triple well' structures needed for that tunneling are created by doping at several different high energy levels to make isolated 3D structures deep into the substrate.
    http://electronicdesign.com/energy/...sh-memory-storage-cell-size-boost-performance

    The process guys tell us what they want and we tell them what works in a practical manner with what we have. :)
     
    Last edited: May 9, 2015
    bug13 likes this.
  8. dl324

    Distinguished Member

    Mar 30, 2015
    3,235
    619
    Spare cells are designed into NAND FLASH so time to single bit failure isn't meaningful. What could happen with NAND FLASH is that capacity will decrease. I don't know how it handles situations where significant storage capacity has failed.

    I recently had the bad experience of buying some counterfeit microSD cards from AliExpress. They take lower density parts and hack them to make them appear much larger. The host system sees the fake capacity and the controller starts overwriting data when real capacity is filled. I'd hope that legitimate devices handled cases where available capacity has been reduced significantly (by protecting the existing data).
     
    bug13 likes this.
  9. dl324

    Distinguished Member

    Mar 30, 2015
    3,235
    619
    Multilevel cell FLASH are pretty interesting too. Micron is up to 3 bits per cell. That takes some pretty accurate charge control. Not like the old days when you just deposited a lot of charge on the floating gate.
     
    bug13 likes this.
  10. nsaspook

    AAC Fanatic!

    Aug 27, 2009
    2,907
    2,163
    For things with tons of error-correction MLC is fine, for embedded memory on die SLC is still the winner.
    http://www.smxrtos.com/articles/mlcslc.htm
     
    bug13 likes this.
  11. bug13

    Thread Starter Well-Known Member

    Feb 13, 2012
    1,208
    38
    Thanks, this is the exactly info I need. I am actually in the process of finding a suitable non-voliate memory for my very long term data logging project.
     
Loading...