I need help implementing a wired-AND bus for a serial pin (MISO pin on a SPI bus). The MISO (Master in/Slave Out) line comes from 3 different devices and there is a pull up resistor on the input to the Master device which is reading the MISO line. On the current schematic it shows the 3 MISO pins from the 3 slave devices connected directly together then sent to the master device board, but the bus isn't working and I'm wondering if the connections are wrong. Anyone ever done a wired-and bus before? Any advice?

 

I need help implementing a wired-AND bus for a serial pin (MISO pin on a SPI bus). The MISO (Master in/Slave Out) line comes from 3 different devices and there is a pull up resistor on the input to the Master device which is reading the MISO line. On the current schematic it shows the 3 MISO pins from the 3 slave devices connected directly together then sent to the master device board, but the bus isn't working and I'm wondering if the connections are wrong. Anyone ever done a wired-and bus before? Any advice?

You don't want a wired AND. What you want is a tri-state bus with the SPI chip select controlling the tri-state enable. Ragardless of how the actual peripheral works this will enforce a controllable bus discipline.

I like the individual active low tri-state buffers like the following from On Semiconductor for this purpose.

http://www.onsemi.com/pub_link/Collateral/MC74VHC1GT125-D.PDF

 

I agree that I don't want one, but whoever wired this up said he used a wired-AND bus, which isn't working. And looking at how he connected it, it seems to me like he doesn't know how to implement a wired-AND bus. I'll probably just end up redoing the whole board anyway...like your quote says.

 

I meant no offense with my comment. It could work but only if the individual peripherals implement it that way. Some SPI peripherals implement the MISO line as driving all the time, which clearly won't work in a wired AND environment. Some SPI peripherals have it go tri-state when SS*(Slave Select*) is inactive. If they did this then it might work if all three SPI peripherals did this.

The only way wired AND could work as intended is if there was a pullup resistor and the three SPI peripherals had open collector(drain) drivers on the MISO line. I personally rate this possibility as exceedingly unlikely since most folks abandoned open collector busses in the mid '70s.

 

since most folks abandoned open collector busses in the mid '70s.

This is inaccurate. I2C and CAN are both open collector, and are very much used in the mid '00s.

 

I was thinking of parallel busses when I made the comment. I yield on I2C being open collector, but its speed is limited because of that fact. On the other hand CAN has a number of configurations on controllers like the SJA1000 and its prececessor the 82C200, including push-pull, pulled up, and pulled down. Used with a transceiver, like the 82C251 it is more correct to call CAN quasi-differential with respect to a common ground.

I never was a big fan of using one active/one passive state on the CAN controller TX outputs. We always used transceivers because we had long cables.

 

I've never used CAN without the one active/one passive state setup. Don't you lose the auto prioritized arbitration feature of CAN when you do that?

 

No offense was taken, sorry if it came off that way.

I think that the slaves are constantly driving the MISO output high, like Papabravo said. I agree that it shouldn't work at all if that is the case. I looked at the VHDL of one of the slaves FPGAs and it doesn't look like it would, but I'm no VHDL expert. All I know is when I try to drive the MISO low I get a current jump that could damage the FPGAs.

 

I've never used CAN without the one active/one passive state setup. Don't you lose the auto prioritized arbitration feature of CAN when you do that?

No you don't, but you probably only use the feature on a controller when it is connected to a transceiver. Dominant is still dominant and recessive is still recessive even with a transceiver. Bitwise arbitration still has to happen in the identifier field regardless of how the physical layer is implemented.