Will this work?

Discussion in 'The Projects Forum' started by Franco_oz, Jan 24, 2009.

  1. Franco_oz

    Thread Starter Active Member

    Jan 12, 2009
    It should be very simple and straightforward but it doesn't do what i thought? I have 4 555 in cascade to control a FF but LTSpice simulation go crazy when i connect the 2 outputs to S and R of my flip flop. Am i doing something wrong or spice need some setting i am not aware of?
    First 555 create a delay for the 2nd one which is just a 1sec pulse to drive set line in my FF and the bottom 555 is the same, create a delay before sending a pulse to reset the FF.
    Why it doesn't work?
  2. Franco_oz

    Thread Starter Active Member

    Jan 12, 2009
    I just wired the rst of each 555 to a rc network to create a power up reset and simulation looks lot better now. Hope it fixed the problem!
  3. bertus


    Apr 5, 2008

    I think C7 will destroy U8 afther some time.
    It is not wise to have a large capacitor at the output of a cmos port.

  4. Franco_oz

    Thread Starter Active Member

    Jan 12, 2009
    Hi Bertus, C7 is there to give me a known state at startup, what else could i do to make it reset when power is applied?
  5. mik3

    Senior Member

    Feb 4, 2008
    A real flip flop IC is designed to drive its Q output always to high for example during power up and thus you don't have to worry about it. If you make the flip flop by using discrete gates then you have to worry about it and race conditions too. I suggest you buy a flip flop integrated in a chip.
    Also, according to the diagram in the pdf, during power up all the 555 will trigger and this is what causes the strange behaviour. The idea of using a capacitor on the reset pin sounds good and clever.
    What is more, C7 will destroy U8 when its output goes low because all the charged stored in the capacitor will rush to ground through the gate's internal transistors.