Will this circuit protect my MOSFET?

Thread Starter

¡MR.AWESOME!

Joined Aug 15, 2010
33
Hey guys and gals. I am curious as to whether this circuit will protect the FET. I am specifically concerned with ceramic capacitor C14. I used the HBM 150pF 330Ohm 25kV with a worst case capacitor bias of 70% (ie: at the ESD voltage, the capacitance will drop to only 30% of it's rated value) to choose the capacitance value. It's an X7R dielectric, btw. The N-MOSFET is this. As you can see, the gate-source junction is protected to 2kV.

I am just curious if C14 will protect the FET from any ESD on the source's pin. I get that the internal protection diodes of the FET will alleviate an ESD event up to 2kV on the GATE, because it will shunt that current to source (which is connected to ground). But what if there is an ESD event on the source pin? The current will be shunted to the gate, right? And then the current will go from there until the charge is dissipated?

The gate is ultimately connected to some external voltage. The drain is connected to a Schmitt trigger input (rated to 2kV ESD). The source goes off the board and then is either connected directly to ground or to a switch that will connect it to ground when activated. It will be handled by a human installer, which is why I want ESD protection on it.

Help me out here. I'm not too sure of myself on this one.
 

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PaulEE

Joined Dec 23, 2011
474
¡MR.AWESOME!;452267 said:
Hey guys and gals. I am curious as to whether this circuit will protect the FET. I am specifically concerned with ceramic capacitor C14. I used the HBM 150pF 330Ohm 25kV with a worst case capacitor bias of 70% (ie: at the ESD voltage, the capacitance will drop to only 30% of it's rated value) to choose the capacitance value. It's an X7R dielectric, btw. The N-MOSFET is this. As you can see, the gate-source junction is protected to 2kV.

I am just curious if C14 will protect the FET from any ESD on the source's pin. I get that the internal protection diodes of the FET will alleviate an ESD event up to 2kV on the GATE, because it will shunt that current to source (which is connected to ground). But what if there is an ESD event on the source pin? The current will be shunted to the gate, right? And then the current will go from there until the charge is dissipated?

The gate is ultimately connected to some external voltage. The drain is connected to a Schmitt trigger input (rated to 2kV ESD). The source goes off the board and then is either connected directly to ground or to a switch that will connect it to ground when activated. It will be handled by a human installer, which is why I want ESD protection on it.

Help me out here. I'm not too sure of myself on this one.
Not sure about the capacitor, but I often see a backwards diode connected between the drain and source to protect high voltages between those pins. Backwards as in cathode to drain, anode to source.
 

Thread Starter

¡MR.AWESOME!

Joined Aug 15, 2010
33
So that would clamp the voltage down to Vd minus the diodes voltage drop, right?

Come to think of it, wouldn't the body diode do the same thing? So a positive ESD event would go from the source to the drain and then whatever was on the drain side would have to deal with the spike. What about a negative ESD pulse?

Clearly, I don't quite know enough to draw any definitive conclusions on this.
 

PaulEE

Joined Dec 23, 2011
474
¡MR.AWESOME!;452286 said:
So that would clamp the voltage down to Vd minus the diodes voltage drop, right?

Come to think of it, wouldn't the body diode do the same thing? So a positive ESD event would go from the source to the drain and then whatever was on the drain side would have to deal with the spike. What about a negative ESD pulse?

Clearly, I don't quite know enough to draw any definitive conclusions on this.
Me neither. :)

Here's how I think of it.

In normal operation, a MOSFET can drive a load with the correct gate signal applied.

If the load happens to be inductive, we know (well, I do, and you will in a minute if you didn't already), from electromagnetics, that the voltage across an inductor is NEGATIVE proportional to the rate change of flux through it.

Basically, if you run a current I through an inductor L, it will generate an electromagnetically-derived field in the inductor. If you were to suddenly take the power supply off and pause time, the field will collapse very quickly - as a result, a very high voltage would appear across the inductor leads, but it would be a negative voltage with reference to the original source. EMF = -d(flux)/dt

In the H-bridge circuit, the bottom diodes on the two bottom transistors protect them from the negative EMF produced upon pulsing the motor coil(s), and the top diodes on the top two transistors protect from large positive EMFs. The gates are generally away from the EMFs and don't need much in the way of protection, but you can use the same scheme for the gates if you'd like. It will affect the input signal to the gate, but not by much.

Does that make a bit more sense?
 

Thread Starter

¡MR.AWESOME!

Joined Aug 15, 2010
33
Yea, I already have some TVS diodes reverse biased on some FET's that run some relays. So that's all good. I just don't know exactly what will happen when an ESD event occurs on the source. It makes sense that since the diode is forward biased in this case that the current would just go from source to drain. I just don't know if such high voltages will cause problems inside the FET. I didn't find anything in my searches about protecting the source from ESD, which tells me that it isn't a concern, but I don't want to assume anything.
 

PaulEE

Joined Dec 23, 2011
474
¡MR.AWESOME!;452294 said:
Yea, I already have some TVS diodes reverse biased on some FET's that run some relays. So that's all good. I just don't know exactly what will happen when an ESD event occurs on the source. It makes sense that since the diode is forward biased in this case that the current would just go from source to drain. I just don't know if such high voltages will cause problems inside the FET. I didn't find anything in my searches about protecting the source from ESD, which tells me that it isn't a concern, but I don't want to assume anything.
It isn't so much the source I worry about, it's the transistor as a whole. For voltage to damage it, the potential difference between any two points is of concern. In your case, you seem to have all points covered. You know?
 
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