Widlar current source design

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laguna92651

Joined Mar 29, 2008
101
I've designed this Widlar current source to deliver 5mA of current. I ran it in pspice, and did a sweep of load resistors from 1 to 2.7kΩ. The current source regulates relatively well from 1 to 900Ω. Two questions; is the design done okay and how do I calculate the range of load resistance for which the design will work? When I breadboard the circuit I will be using a CA3046 transistor array.
Thanks
 

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JDT

Joined Feb 12, 2009
657
s the design done okay
Thanks
Well, you wanted 5mA and from your diagram you are only getting 827uA so you have not met your objective!

This is caused by the value of R2 which should be lower (or even zero).

If R2 is zero and the transistors are identical, then it should be close to a 1:1 current mirror. Have you simulated this!
 

Jony130

Joined Feb 17, 2009
5,487
Form CA3046 datasheet we can read that Vbe=0.775V for 5mA and Hfe≈100.



So we start the calculations;

R1=(Vcc-Vbe)/(Ic+2*Ib)=(10V-0.775V)/(5mA+100uA)=9.225V/5.1mA=1.8088KΩ

And If we assume saturation Vc=Vb then
Rload_max=(Vcc-Vbe)/Ic=1.845K

But in discrete circuit we must add emitter degeneration resistors.



We pick R2,R2 that voltage drop is equal 0.1V..0.5V.

So
R2=R3=0.2V/5mA=39Ω

And R1=(Vcc-Vbe-0.2V)/5.1mA=1.769KΩ≈1.8KΩ

and Rload_max=1.8KΩ
 

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Thread Starter

laguna92651

Joined Mar 29, 2008
101
It was my mistake the pspice schmatic I uploaded had been set up to sweep the load so the current values were not for a given load. See updated schmatic. When I entered your design in pspice I didn't get Io=5mA, did I do something wrong? What is the advantage of using Vcc=10v versus ±5v? In your design why did you pick a voltage drop of .1 to .5v across R2? You showed Rload_max=1.8K, are you saying Rload_max=R1?

Using your calculations in my design, I also get 1.845kΩ for Rload_max, but when I sweep the load in pspice, it starts to lose regulation around 900Ω. See DC Sweep file in initial post. How would I determine the min Rload? The current source has to be a Widlar current source.
Thanks
 

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Jony130

Joined Feb 17, 2009
5,487
Hmm, If you use single supply (Vcc=10V) then R4 must by connect to Vcc.
And for split (symmetrical) supply ( ±5V) R4 can be connect to Vcc or to GND.
And Rload_min=0
 

Thread Starter

laguna92651

Joined Mar 29, 2008
101
I haven't had a chance to try it, but when I built your design Rload was connected to ground not Vcc. Why is my calculation for Rload_max (1.8K) so far off of the pspice results (900Ω)?
 

Jony130

Joined Feb 17, 2009
5,487
Why is my calculation for Rload_max (1.8K) so far off of the pspice results (900Ω)?
Because you don't understand how this sample circuit work.
And I doubt whether you understand how BJT work.
Nevertheless, if you connect R4 to GND then Q1 and R4 is supply only form V2 voltage source, and by that
Rload_max=(V2-Vbe1)/Ic=(5V-0.75V)/5mA=4.25V/5mA=850Ω
 

Jony130

Joined Feb 17, 2009
5,487
Yes you can use Vce2sat=0.2V instead of Vbe.
But I defined that saturations starts if voltage on collector is equal voltage on base.
And that is why I use Vbe. By doing this I make the error in a "safe way".
 

hgmjr

Joined Jan 28, 2005
9,027
Yes you can use Vce2sat=0.2V instead of Vbe.
But I defined that saturations starts if voltage on collector is equal voltage on base.
And that is why I use Vbe. By doing this I make the error in a "safe way".
My understanding of BJT based current mirrors is that the transistor with its base and collector tied together can never saturate so the use of Vbe is correct. Using Vce(sat) would yield an error in the current calculation.

hgmjr
 

Ghar

Joined Mar 8, 2010
655
My understanding of BJT based current mirrors is that the transistor with its base and collector tied together can never saturate so the use of Vbe is correct. Using Vce(sat) would yield an error in the current calculation.

hgmjr
You're right as far as I understand it...

Vce = 0.2 comes from the BC junction having a smaller forward voltage than the BE diode.

Vbe = 0.7, Vbc = 0.5
And of course Vce = Vbe - Vbc = 0.2

If you connect base and collector you force Vbc = 0 and then Vbe = Vce

In this case though, we're worried about the output transistor which isn't in that condition. There you want to keep the BC junction reverse biased, or something like Vbc < 0.3 meaning Vce > 0.4
 
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Jony130

Joined Feb 17, 2009
5,487
Hmm, but the "output" BJT can easily be saturated.
And I was talking about Rload_max and "output" BJT.
And we can not saturated a BJT connected as a diode because we cannot saturated a diode.
 

hgmjr

Joined Jan 28, 2005
9,027
Hmm, but the "output" BJT can easily be saturated.
And I was talking about Rload_max and "output" BJT.
And we can not saturated a BJT connected as a diode because we cannot saturated a diode.
It was not clear to me from the discussion that the output transistor was the one being discussed. I thought the diode connected transistor's behavior was the one of concern.

I agree that the output transistor can be easily saturated if the current mirror is set to provide enough current.

hgmjr
 
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