This is a conventional cascode configuration amplifier:

Here is an excerpt in "Self-biased cascode RF power amplifier in sub-micron technical field" .
http://www.google.com.vn/patents/US6515547

In state of the art MOS power amplifiers, the drain-gate voltage can often go as high as three times the supply voltage. This poses a limitation on the maxi-mum supply voltage that can be used in such amplifiers and still avoid gate-drain breakdown. One method of ameliorating this problem is to utilize the familiar cascode structure in the amplifier, in which, in a two-transistor example, one transistor is in the common-source configu-ration and another is in the common gate configuration. In such cascode configuration the signal swing drops be-tween the two transistors and therefore lessens the gate to drain breakdown problem. Such cascode transistors appear as a four terminal device: two gates, one source
and one drain.

I don't understand why the cascode configuration can solve the problem gate-drain breakdown. Please explain.

 

Simply don't believe in every word you read in the internet. For sure we can split Vdd into two Vds junction. Or we can use low power MOS as a M1 and high power MOS (M2). We use cascode configuration because this configuration eliminates the Miller effect.

 

Thank you, Jony.
You remind me about eliminating Miller effect. That was my confusion but I didn't know how to search for it.
Can I ask you some questions?
Are Lg1, Rg1, Lg2, Lg2, and Ls1 parasitic parameters of transistor?
About Miller effect, do you agree with the answer here?
http://electronics.stackexchange.com/questions/69300/how-does-a-dual-gate-mosfet-reduce-miller-effect

 

Are Lg1, Rg1, Lg2, Lg2, and Ls1 parasitic parameters of transistor?

I don't think so

About Miller effect, do you agree with the answer here?
http://electronics.stackexchange.co...-does-a-dual-gate-mosfet-reduce-miller-effect

What is the voltage gain of a M1 transistor?
http://forum.allaboutcircuits.com/showthread.php?p=614708#post614708

 

I don't think so

I am confused because their symbols.

What is the voltage gain of a M1 transistor?

I knew Miller effect but I want to know whether you agree with answers in the page above about how cascode configuration reduces Miller effect.

 

I am confused because their symbols.

I think that those symbol represent real components not parasitic parameters.

I am confused because their symbols.

I knew Miller effect but I want to know whether you agree with answers in the page above about how cascode configuration reduces Miller effect.

cascode configuration reduces Miller effect by a reduction M1 voltage voltage.
M1 gain = (1/gm2)/(1/gm1) = gm1/gm2
Also M2 work as a common gate configurations the Miller Cgd multiplicative effect does not exist. Because gate is short to GND for AC signal.