Why IEEE vhdl standard library is not STL?

Discussion in 'General Electronics Chat' started by jcyang, Jan 19, 2010.

  1. jcyang

    Thread Starter New Member

    Jan 18, 2010
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    IEEE vhdl language reference manual only defined a limited set of standard packages.And it do not defined the functionalities on the standard types,such as STD_LOGIC.So there are no standard AND2, INV components/operator.

    It seems that Altera's MAX+Plus II do not support AND2(and gate), INV (inverter),components(if there are,please feel free to correct me),but Xilinx Foundation does.

    Why IEEE vhdl standard library could not become something like STL in the C++ world?

    thanks.
     
  2. Papabravo

    Expert

    Feb 24, 2006
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    Because many people do not like for other people to tell them what to do or how to do it. The folks at Xilinx and Altera are no exception. They have the courage and the confidence to promote different ideas so they can stand or fall on their own merits in the marketplace. Some IEEE standards are widely adopted and others are routinely ignored.

    As an example suppose I said that the cost of making an AND2 structure in an FPGA was 1.0 and the cost of making an AND8 was 0.1, then how many AND2 stuctures would be in the floorplan versus how many AND8 structures. So I ask you, is an AND8 with 6 inputs tied high the same as an AND2 with no extra inputs hanging around. I think we both know the answer, and it is that we can't always have what we want.
     
  3. jcyang

    Thread Starter New Member

    Jan 18, 2010
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    My thoughts here:
    Because fpga design software is high related to the targeted chip and there are only two enterprise capable to develop such software.Altera's Max+PlusII could only support chips ship from Altera,so does Xilinx.These vendor control the whole progress of fpga design,from software to hardware.Then they tends to develop specific feature targeted on they own platform.So IEEE standard library could not be something like STL in the C++ world.

    AND2 is primitive of Altera Max+PlusII,but it is not primitive of Xilinx Webpack.Actually we could desing our own component AND2(which Xilinx choose to provide it within unisim package,but we choose not to load thi package).
    INV is not primitive of Altera Max+PlusII,neither Xilinx WebPack.
     
  4. Papabravo

    Expert

    Feb 24, 2006
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    The situation you refer to is vertical integration, where a company that makes chips realizes they can sell more chips by becoming a software company. So they develop software that services their product line and price it or give it away to serve their interests. Standards seldom serve their interests in this regard.

    It is interesting to note that few if any software companies have succeeded in selling more software by going into the chip business.

    I guess that is the way the Mercedes Benz --- ahhhh cha cha cha!
     
  5. lmartinez

    Active Member

    Mar 8, 2009
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    It is a mutual agreement among the majority. In another words if you are not part of it, get out.........It sort of resembles the history of the FOUNDATION OF THE USA .............." Freedom of religion"
     
  6. Papabravo

    Expert

    Feb 24, 2006
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    As a member of more than one standards committee in the past 40 years I can testify to the problem of convincing a company to put aside it's parochial interest for the common good. It is an extraordinarily difficult feat to accomplish.
     
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