It is okay means perfect PWM.

What I care about was the deadtime, you didn't show that, or you thought that you can handle it?

 

Normally when in parallel the capacitors then the capacitance will be getting bigger, so the switching frequency will be lower, this is the normal issue or has some other reasons cause that and not follow the normal calculation?

How do you expect the combined gate capacitances to affect the frequency generated somewhere the other side of that gate driver?!