why HIGH Level Output Current is negative

Discussion in 'General Electronics Chat' started by alitex, Jul 28, 2010.

  1. alitex

    Thread Starter Active Member

    Mar 5, 2007
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    what the meaning of this
    HIGH Level Output Current = -0.4 mA in OR gate(7432)

    many thanks
     
  2. Papabravo

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    Feb 24, 2006
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    It means that current flows out of the output and into the load. A positive current flows into a load. If you want to use the opposite sign convention you can, but you have to be consistent
     
  3. Ron H

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    Errmm... that's inconsistent.:confused:
     
  4. alitex

    Thread Starter Active Member

    Mar 5, 2007
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    why it's negative?
    i think the current when flows out through the load the polarity is from positive to negative,or not???
     
  5. Norfindel

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    Mar 6, 2008
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    Tell us where are you reading this, so that we can take a look.
     
  6. Ron H

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    I found one explanation (BrianG's post, about halfway down the page). It seems a little weak, but it goes like this:
    Early logic gates (RTL, DTL) had no active pullup. The devices were often open collector, in order to facilitate wired-AND functions. As such, the gates themselves could only sink current, and the specification was, by default, a positive number. When TTL added active pullups, the sourcing current was in the opposite direction of the sinking current, and so was assigned a negative value.
     
  7. Ron H

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    I think you will find that all TTL datasheets use this convention. See specs for IOH and IOL.
     
  8. Papabravo

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    Feb 24, 2006
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    No it is not inconsistant at all. It is negative as it leaves the source and changes sign as it goes into the load. If the node is any point on the conductor between the source and the load then KCL is satisfied because the sum of the currents is zero. Try reading what I wrote one more time with feeling.

    You are correct about the adoption of a single convention for early TTL, and maybe RTL and DTL datasheets too, where a source current had a negative sign and a sink current had a positive sign. This convention also carries over to present day CMOS logic which tends to have symmetrical drive unlike TTL outputs which could usually sink way more current than they could source.

    Nothing would change however if you chose to adopt the alternate convention.
     
  9. Ron H

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    The OP wrote:
    Your first statement says the load current is negative:
    Your second statement says the load current is positive:
    Maybe I am misinterpreting your comments, but I thought your second comment contained a typo.
     
  10. Norfindel

    Active Member

    Mar 6, 2008
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    You're right. I didn't noticed. Never used TTL ICs much.
    Your explanation up there is convincing, as the current with the output high is quite pathetic, so it certainly looks like it doesn't have an active output when high. Still, it's a mess to use negative current when the output is high.
    In the HCT part, the outputs have +/- in high and low. I guess that allows you to source or sink current in any output value (for example: an output connected to a voltage below gnd thru a resistor will always source current).
     
  11. Papabravo

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    Feb 24, 2006
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    The sign change happens in a "node" right on the wire between the source and the load. It just so happens that this "node" has only two branches. The current is negative coming coming out of the HIGH output and into the "node". It changes sign and becomes positive going from the node into the load. Apply KCL to the node and a positive current and a negative current sum to zero and all is right with the world. At least that is the way I'm looking at it. Your mileage may vary.
     
  12. alitex

    Thread Starter Active Member

    Mar 5, 2007
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    we know that the current when flows out through the load the polarity is from positive to negative,and we can consider TTL logic as same as any electronic passive element relatively flow current...
     
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