What the future of cache memory?

Discussion in 'General Electronics Chat' started by Hayder, Mar 9, 2016.

  1. Hayder

    Thread Starter New Member

    Mar 6, 2016
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    Hi;
    Cache memory invented cause there is a huge different speed between CPU and the rest of PC components including main RAM.

    But now a days , the speed of RAM DDR4 speed is about 2133Mhz and this is more than CPU speed ( even there is 3200MHz)!!

    So is the speed of RAM change the future of CPU ? or cache is a must because it lie on CPU die and that prevent the need of external connections?
     
  2. nsaspook

    AAC Fanatic!

    Aug 27, 2009
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    The main difference between main RAM and cache RAM is memory Latency in cpu cycles. It's not just how fast the data can be transferred but how long it takes for the first byte of data to be delivered to the CPU execute engine. While external RAM speed has gotten faster, Latency measured in real time (nanoseconds) hasn't changed significantly over the past decade.

    Latency speed examples from www.7-cpu.com :

    Intel Sandy Bridge

    • L1 Data Cache Latency = 4 cycles for simple access via pointer
    • L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
    • L2 Cache Latency = 12 cycles
    • L3 Cache Latency = 27.85 cycles
    • RAM Latency = 28 cycles + 49 ns (for open RAM page). RAM page size = 16 KB?
    • RAM Latency = 28 cycles + 56 ns (for random RAM page).
    Intel Haswell
    • L1 Data Cache Latency = 4 cycles for simple access via pointer
    • L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
    • L2 Cache Latency = 12 cycles
    • L3 Cache Latency = 36 cycles
    • RAM Latency = 36 cycles + 57 ns
    Intel Skylake
    • L1 Data Cache Latency = 4 cycles for simple access via pointer
    • L1 Data Cache Latency = 5 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
    • L2 Cache Latency = 12 cycles
    • L3 Cache Latency = 42 cycles (core 0)
    • RAM Latency = 42 cycles + 51 n
    http://www.extremetech.com/extreme/...-why-theyre-an-essential-part-of-modern-chips
    [​IMG]
     
    Last edited: Mar 9, 2016
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  3. Hayder

    Thread Starter New Member

    Mar 6, 2016
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    Its huge difference between cache and RAM, but the difference between the 3 CPUs is just in L3?
     
  4. nsaspook

    AAC Fanatic!

    Aug 27, 2009
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    I'm sure there are some design changes in the L3/L4 to main memory architecture with each type of cpu as the external memory type and speeds change. The L1 and L2 core Cache Latency is optimized to its core.
    [​IMG]
    [​IMG]
     
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  5. Hayder

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    Mar 6, 2016
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  6. hp1729

    Well-Known Member

    Nov 23, 2015
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    How far into the future are we looking at? Wafer Scale Technology? We get rid of cache as well as rotating media and put the whole system on one wafer?
     
  7. dl324

    Distinguished Member

    Mar 30, 2015
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    Performance. Microprocessor manufacturers wouldn't use die area for big caches if the ROI didn't beat every other performance enhancement they had in their bag of tricks.
     
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  8. Hayder

    Thread Starter New Member

    Mar 6, 2016
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    That's great my friend, that's clear, thanks for your help.
     
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