they are pnp & npn..... anyways i will check with separate base transistors for any improvements. V1 is just some old rechargeable AA cells i have they don't give much high currents.

Imagine how the diode junctions are oriented in each transistor, then try to figure out what kind of current will be flowing through the bases.
I learned this the hard way in my early days. The transistors being in TO-3 package they stood up to that punishment, but the transformer in the power supply wasnt too happy about it.

 

As I said earlier, you need a common emitter stage between the output of the 555 and Q1 &Q2. It is essential that Q1 and Q2 are driven from an output that can swing close enough to the supply rails to ensure that each transistor can switch fully off while the other is fully on. I don't think that the 555 output can do this.

True. With a 5V supply the 555 output will only go to about 3.5V. An alternate way to drive the transistors is to place two diodes in series with the Q2 PNP transistor base resistor. That way Q2 will turn off with a 3.5V input. To minimize leakage you could also add a 10k resistor between Q2's base and emitter.

 

That's obvious from the schematic. Did I post something to make you think that I didn't understand that?

no, it's me who doesn't understand how both transistors will be on at the same time for a distinct high or low signal. unless u explain the reason, i m not sure i will be able to understand everything u say from my level.

As I said earlier, you need a common emitter stage between the output of the 555 and Q1 &Q2. It is essential that Q1 and Q2 are driven from an output that can swing close enough to the supply rails to ensure that each transistor can switch fully off while the other is fully on. I don't think that the 555 output can do this.

another transistor, hmmmm. i think 555 op was swinging very close to supply, but i will check.

 

no, it's me who doesn't understand how both transistors will be on at the same time for a distinct high or low signal. unless u explain the reason, i m not sure i will be able to understand everything u say from my level.

If you look at the circuit with only one resistor, there is a direct path from the emitter of Q2 through its base to the base-emitter of Q1 with nothing to limit the current. Thus the base current of both transistors will be very high, independent of the 555 output, and likely zap the transistors in real life.
Observe the base current in the simulation of that circuit and you will see.
That's why you need two separate resistors, one to each base.

another transistor, hmmmm. i think 555 op was swinging very close to supply, but i will check.

The NE555 is an idealized behavior model which does not accurately model the real device's output voltage swing (which actually only goes to about 3.5V with a 5V supply). That's why you need to add a transistor driver or a couple diodes as I stated in post #22.
Here is a 555 LTspice model I put together which more realistically simulates the output voltage.

 

@crutschow
thanks, that was helpful.

i just checked the 555 o/p in ltspice, it's swinging by the rails alright. weird. why would they put in an ideal model that doesn't follow the datasheet.

 

why would they put in an ideal model that doesn't follow the datasheet.

Because it is much easier to make it work good enough than to implement all kinds of borderline and likely undocumented behavior.
Simulation is allways only as good as the model, and perfect models are hard to make. Also you should realise that the borderline behavior will likely be different with each brand of the chip.

 

..............................
i just checked the 555 o/p in ltspice, it's swinging by the rails alright. weird. why would they put in an ideal model that doesn't follow the datasheet.

If you look at the model description it states it's an "idealized 555 timer model", and arguably an ideal version of the 555 would have the output going to the rails. That's why it's generally preferable to use the transistor level model which should be much closer to the real device (typical) characteristics.
Note that the CMOS version of the device does go to the rail with no load (but of course drops with any appreciable load current).

 

ok, after reading carefully all the above, i made this following diagram. with given load it reaches ~9.6v / 19mA. but,

-> the o/p of upper push-pull is less than lower one,
-> lower push pull o/p is noisy.
-> & not sure what should be ideal values for base resistors to separate then properly. upping their values lower the o/p of push pulls.