I know that the design fig.2 safes battery more than fig1, and that have greater input impedance?​

Are there differences that are more important?​

Thank you​

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You could save even more battery by unplugging them both, since they don't appear to do anything.

 

You could save even more battery by unplugging them both, since they don't appear to do anything.

thank you wayneh for fast reply
My question is what is the difference between the two designs, one of them has (1mA, 1.5V) operating point and the other has (0.1mA, 1.5V) operating point?

 

Wayneh is saying that the circuits shown do nothing, so they have no value. If you want comments add inputs and loads.

 

Assuming it's used to actually supply a load at node #1, figure 2 would have a much higher output impedance.

 

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Yes, I know that the circuit does not do anything
These days, I'm studying transistor circuit design to amplify signals
On any base or on what basis is operating current selected at a certain value?
It may be 100mA, 10mA, 1mA or even 0.1mA
I understand that the value of VCE must be equal to half the value of the battery in order to get the symmetric swing of a resulting signal?

 

The current is selected at the right level to drive the next stage properly.
and, no, setting the collector voltage at 1/2 Vcc is just a little bit off for the best symmetry. The transistor will always need a little bit of voltage so the proper set point is a little higher than 1/2 Vcc. The "little bit" depends on how much current you are using, but the basic premise is that the transistor never completely uses up zero volts.

 

The current is selected at the right level to drive the next stage properly.

Isn't each stage has its own biasing?

and, no, setting the collector voltage at 1/2 Vcc is just a little bit off for the best symmetry. The transistor will always need a little bit of voltage so the proper set point is a little higher than 1/2 Vcc.

are you mean because at saturation VCE not = 0, it is approx 0.4Volt?

The "little bit" depends on how much current you are using, but the basic premise is that the transistor never completely uses up zero volts.

Are there any relation between ICQ and VCE sat?

thank you
This is the first response enters into the heart of the matter

 

1) Even if the next stage has its own VOLTAGE biasing (and some of them don't), it still needs some current from the stage before it. Much like this stage that you presented, it is sitting there waiting for instructions, and whatever you want it to do will require a little bit of current to change the base current from what it is biased for. In a low voltage gain, high current stage, it will need quite a lot of current from the stage before it.

2) Right. If the transistor saturates at .4 volts, you will get the best symmetry at 1/2 Vcc + .4 volts. It is as if that last .4 volts is never available for the output. In fact, the gain of the transistor decreases as it gets near saturation and that causes distortion in the output. You would bias the collector voltage even higher when distortion is important to avoid.

3) Yes. If your (amps collector quiescent) is more, the Vce Sat of the transistor is higher. The datasheets go into great detail about how close to zero each transistor type can get if the ICQ is 10 ma, 100 ma, 1000 ma. It is best when a graph is supplied, but some datasheets only give a few data points.

 

Another difference would be... Let's say this is to be used as a common-emitter amplifier. The higher current design will have more bandwidth due to the lower impedances involved. Frequency response is typically dominated by node impedance, device capacitance, etc. Given the same device and parasitic capacitance, the lower impedance circuit will have more bandwidth.

 

1) Even if the next stage has its own VOLTAGE biasing (and some of them don't), it still needs some current from the stage before it. Much like this stage that you presented, it is sitting there waiting for instructions, and whatever you want it to do will require a little bit of current to change the base current from what it is biased for. In a low voltage gain, high current stage, it will need quite a lot of current from the stage before it.

Suppose that the second stage is another common emitter config. (not emitter follower), and suppose that one of the above circuits is intended to preamplify a Mic signal (about 10 mV peak). The designer can choose some value large or small for ICQ. On what basis the designer take a big or small value,,,, ??

2) Right. If the transistor saturates at .4 volts, you will get the best symmetry at 1/2 Vcc + .4 volts. It is as if that last .4 volts is never available for the output. In fact, the gain of the transistor decreases as it gets near saturation and that causes distortion in the output. You would bias the collector voltage even higher when distortion is important to avoid.

In this way may get faster to the cutoff region?

3) Yes. If your (amps collector quiescent) is more, the Vce Sat of the transistor is higher. The datasheets go into great detail about how close to zero each transistor type can get if the ICQ is 10 ma, 100 ma, 1000 ma. It is best when a graph is supplied, but some datasheets only give a few data points.

Yes it s for 2n3904 approx 0.05 volt @ IC = 1mA and 0.075 @ IC = 0.1mA


Finally, I've seen many designs that perform the same function for almost similar circuits, some uses large ICQ, others small.

thanks

 

1) Consider that the next stage is coupled with a capacitor into the base and 2 resistors to set the bias point. Those two resistors diminish the amplitude of the driving signal. You pick the current in the first stage so that the loss of amplitude into the biasing resistors is small enough to be acceptable. That might be 2% loss of gain or 20% loss of gain. It depends on your purpose.

2)Yes, but you generally don't want to get all the way to cutoff. It causes distortion unless you are doing square waves on purpose.