What is a 'Clock repeater' ?

Discussion in 'General Electronics Chat' started by PauloConstantino, Sep 8, 2016.

  1. PauloConstantino

    Thread Starter Member

    Jun 23, 2016
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    5
    Dear all,

    I have been reading some parts of the book High-speed digital design, and I've met a paragraph where he speaks about how a clock's duty cycle changes as it passes through a chain of 'clock repeaters'.

    Can someone please tell me what a clock repeater means? I think he means gates but I'm not sure about this terminology!

    Thanks a lot
     
  2. Bernard

    AAC Fanatic!

    Aug 7, 2008
    4,172
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    We need a mind reader for this one, but my take supposes a long string of LEDs driven by 8 stage shift registers,
    SR. About 37 SRs may need a clock repeater for every 5 SRs. To save a wire, clock repeaters are cascaded so that after 8th clock repeater ( non inverting amplifier ) there might be a microsecond dif. between first & last ??
     
  3. SLK001

    Well-Known Member

    Nov 29, 2011
    817
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    Digital devices have a finite number of devices that they can drive. If many devices need a clock, then a "repeater" is used to increase the number of devices that can be clocked. Say the first clock has a fan-out of 10 devices. The tenth device is a repeater, which can drive another 10 devices, and so on. The duty cycle doesn't change, but the timing does due to the propagation delay through the clock repeater. It is usually nanoseconds, so usually isn't too big of a problem.
     
  4. PauloConstantino

    Thread Starter Member

    Jun 23, 2016
    121
    5
    Thanks guys.

    @SLK001 : He did mention that a single gate usually has different rise and fall times and hence why duty cycles change after a clock signal passes through most gates!
     
  5. dl324

    Distinguished Member

    Mar 30, 2015
    3,242
    619
    Perhaps if you gave more of the context in which the phrase is used, we could guess at what he meant.

    In large, high speed circuits, you need to worry about jitter caused by clock edges arriving at different parts of the circuit at different times. The usual way to address this is to design a clock network (tree) where buffers (repeaters?) are sized relative to the length of the clock net they drive so that clocks arrive in various regions at the "same" time.
     
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