I just saw this as an ad, and I got interested in knowing what it does.

I tried simulating it in multisim with 2n3904's and some 1K resistors, but nothing interesting happened.

When the voltage flows to the base of Q1, it will allow it to conduct, so Q2 would start conducting, which would shut off Q1 because there is less resistance so the base voltage of Q1 drops... ???

Wouldn't this circuit oscillate or turn on and off rapidly?

 

I just saw this as an ad, and I got interested in knowing what it does.

I tried simulating it in multisim with 2n3904's and some 1K resistors, but nothing interesting happened.

When the voltage flows to the base of Q1, it will allow it to conduct, so Q2 would start conducting, which would shut off Q1 because there is less resistance so the base voltage of Q1 drops... ???

Wouldn't this circuit oscillate or turn on and off rapidly?

Looks like a constant current source to drive the load.

 

+1. Constant current source.

For example:

R1 = 56kΩ
R2 = 820Ω
VDD = 10V
R_LOAD = 0 - 2kΩ
I_LOAD = 1mA

 

How did you come up with those values, and could someone explain what it's actually doing then, like what's happening in the circuit/how does it work.

 

How did you come up with those values, and could someone explain what it's actually doing then, like what's happening in the circuit/how does it work.

I am guessing chips started out with an assumption of 10 volts and an assumption of 1mA. He worked back from there.

 

chips just used a simulator and took 1mA into a 1kΩ load as a good place to start.

chips then play around with R1 and R2 until 1mA was achieved.

In retrospect, chips just used a generic NPN transistor. With the 2N3904 specified, the current was 0.86mA.

 

But could someone explain the circuit itself. I'd like to understand how it works and what's happening to make it produce a constant current.

 

The majority of load current is provided via Q1. Q2 only serves to control base current for Q1 and thus sources much less current. Q2 is off until load current (Iload) is such that Iload*R2 = VBE(Q2turnon) ~= .7V. At this load current, Q2 conducts with current IC(Q2) = GM(Q2)*VBE(Q2) = GM(Q2)*R2*Iload. When Q2 turns on, current from Q1's base is diverted, thus throttling Q1 and preventing it from sourcing more current. Thus, the current is regulated at approximately:

Iload ~= .7/R2.

 

Q1 is an NPN emitter follower (or common collector current amplifier).
It is biased in the linear region using R1.

The current to the R_Load flows through Q1 and R2.
R2 is called the current sense resistor. The objective is to maintain a constant current through R2 and hence a constant voltage across R2 of about 0.7V

Q2 is the current sense feedback to the base of Q1.
Q2 is also biased in the linear region.
If the voltage across R2 tries to rise about the quiescent 0.7V, Q2 will conduct more current, reducing the bias on the base of Q1. This reduces the current through Q1 thus bringing the current through R2 back to the specified level.

Thus Q2 provides negative feedback to Q1.

As with all constant current sources, this works for all increasing load resistances starting from 0-ohms so long as there is enough supply voltage. As the load resistance rises, the available supply overhead voltage must be high enough to overcome the resistance.

As a first iteration, you need 10V to supply 1mA into a 10kΩ load.
When you account for the voltage drop across Q1 and R2 the maximum load resistance is lower than 10kΩ, maybe 5kΩ.

Edit: Brownout beats me to it.