What are the layout constraints that need to be followed while laying out a PLL?

Discussion in 'Analog & Mixed-Signal Design' started by SDSI, Sep 17, 2016.

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  1. SDSI

    Thread Starter New Member

    Sep 16, 2016
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    What are the layout constraints that need to be followed while laying out a PLL?
     
  2. Alec_t

    AAC Fanatic!

    Sep 17, 2013
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    They would obviously depend on whether the layout is at the silicon level, board level, or whatever. You need to provide more info.
     
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