Hi,

I have found the Voltage Controlled Voltage Source (VCVS) & Voltage Controlled Current Source (VCCS) in Advanced Design System simulation and trying to understand how it works in modeling a circuit. I have attached the help file explanation. Anyone have any idea how it works and what are the differences between VCVS and VCCS?

Is the VCVS and VCCS available in LTspice for modeling purpose?

Regards,
lkgan

 

Voltage Controlled Voltage Source ≈ opamp
Voltage Controlled Current Source ≈ transconductance amplifier.

And yes you can find VCVS and VCCs in Ltspice.
Type "E" in part search for VCVS
and type "G" for VCCS

 

Voltage Controlled Voltage Source ≈ opamp
Voltage Controlled Current Source ≈ transconductance amplifier.

And yes you can find VCVS and VCCs in Ltspice.
Type "E" in part search for VCVS
and type "G" for VCCS

What is a transconductance amplifier? When we use VCVS, R1 is set to 1e100Ω and R2 is set to 0Ω. On the other hand, when we use VCCS, R1 and R2 are set to 1e100Ω. Do you have any idea what is that settings mean? Sorry, I really can't understand from the help description, hope anyone who knows can explain more. Thanks.

 

What is a transconductance amplifier?

VCCS is a transconductance amplifier.
Simply you put 1V for input and you get 1A of a output current.
So the gain gm = Iout/Vin = 1 Siemens
Do you understand the different between current source, and voltage source ?
An ideal current source is a circuit element where the current through it is independent of the voltage across it.
Here you have the examples of a ideal voltage source and ideal current source.

When we use VCVS, R1 is set to 1e100Ω and R2 is set to 0Ω. On the other hand, when we use VCCS, R1 and R2 are set to 1e100Ω. Do you have any idea what is that settings mean? Sorry, I really can't understand from the help description, hope anyone who knows can explain more. Thanks.

As for R2
In circuit theory internal resistance of a ideal voltage source is equal 0Ω (place in series with voltage source).
And internal resistance of a ideal current source (place parallel to current source) is is ideally infinite .
And R1 determined input resistance of a "control unit".

 

A VCCS (ideal transconductance amplifier) has a current output controlled by a voltage input. The input and output output impedances are both ideally infinite, and for your model they are made very big: 1e100Ω. (There can be difficulties in simulation if they are actually made infinite.)

A VCVS (ideal voltage amplifier) has a voltage output controlled by a voltage input. The input impedance is ideally infinite, but the output impedance is ideally zero, so your model can have zero output resistance.

 

VCCS is a transconductance amplifier.
Simply you put 1V for input and you get 1A of a output current.
So the gain gm = Iout/Vin = 1 Siemens
Do you understand the different between current source, and voltage source ?
An ideal current source is a circuit element where the current through it is independent of the voltage across it.
Here you have the examples of a ideal voltage source and ideal current source.


As for R2
In circuit theory internal resistance of a ideal voltage source is equal 0Ω (place in series with voltage source).
And internal resistance of a ideal current source (place parallel to current source) is is ideally infinite .

Ok, I understand what you mean for above statements.
In the following statement, how do R1 affects the output which act as a "control unit"? For example, for VCVS, if I reduce the value of R1, will I get a lower output voltage? What's the relationship?

And R1 determined input resistance of a "control unit".

 

A VCCS (ideal transconductance amplifier) has a current output controlled by a voltage input. The input and output output impedances are both ideally infinite, and for your model they are made very big: 1e100Ω. (There can be difficulties in simulation if they are actually made infinite.)

A VCVS (ideal voltage amplifier) has a voltage output controlled by a voltage input. The input impedance is ideally infinite, but the output impedance is ideally zero, so your model can have zero output resistance.

Thanks for the clarification.

Adjuster & Jony130,

I have attached the VCO modelling, two questions arise:

1) What is the purpose of setting G = -1? Is it just to invert the gain?

2) The function of VCO is to convert voltage to frequency, why would the modeling convert from voltage to current, charge the capacitor, and convert from voltage to voltage? Why can't just have one VCVS?

 

Thanks for the clarification.

Adjuster & Jony130,

I have attached the VCO modelling, two questions arise:

1) What is the purpose of setting G = -1? Is it just to invert the gain?

2) The function of VCO is to convert voltage to frequency, why would the modeling convert from voltage to current, charge the capacitor, and convert from voltage to voltage? Why can't just have one VCVS?

1) Yes, I would think that this is to give an inversion.

2) Feeding the capacitor from a VCCS creates an voltage related to the time integral of the input voltage. The subsequent VCVS provides a buffered output so that any impedance connected to the VCVS output will not affect the capacitor voltage. A single VCVS will not do this.

 

In the following statement, how do R1 affects the output which act as a "control unit"? For example, for VCVS, if I reduce the value of R1, will I get a lower output voltage? What's the relationship?

Well I hope that this diagram explain everything.

PS the gain is equal 10

 

1) Yes, I would think that this is to give an inversion.

2) Feeding the capacitor from a VCCS creates an voltage related to the time integral of the input voltage. The subsequent VCVS provides a buffered output so that any impedance connected to the VCVS output will not affect the capacitor voltage. A single VCVS will not do this.

Great, I think I get the idea. Thanks! To further analyze the VCO modeling, since the G is -1, it means that the current flow direction should be opposite of what is shown in the picture and charge the capacitor Ci right?

By the way, do you have any idea why would we need to model the VCO with an integrator?

 

Well I hope that this diagram explain everything.

PS the gain is equal 10

Where is the gain = 10 for? Ok, that's a clear illustration. So the source resistance doesn't give a significant impact on the load voltage drop since its' resistance is small as compare to the load resistance.

 

The circuit you have shown appears to be part of a bigger system. The capacitor value also appears to be voltage variable - perhaps a model of a varactor diode?

Do you have details of the remainder of the circuit?

 

No, it's not a varactor diode. The VCO is part of the PLL system. Before the VCO, it's connected to loop filter, and after the VCO, it's connected to divider. As you can see in the attachment, the formula for Ci is 1/(2*pi*Hz_per_Volt). The Hz_per_Volt is the gain, Kv value of VCO,

 

Where is the gain = 10 for? Ok, that's a clear illustration. So the source resistance doesn't give a significant impact on the load voltage drop since its' resistance is small as compare to the load resistance.

Well not exactly.
For example if we have VCVS with gain = Vin/Va = 10V/V
And we have a "control" voltage equal 1V and Rs=2K, and we want 10V across Rload resistor.
And now if we connect VCVS with input resistance low (compare to Rsource). We don't get 10V on the output becaues the load effect of our VCVS input resistance.

So the "equivalent" of a voltage gain is equal
Au = 3.33V/1V = 3.33V/V (but we want gain to be equal 10).

But if we chose R1>>Rsource

Surprisingly we get almost 10V across the load

 

Great, I think I get the idea. Thanks! To further analyze the VCO modeling, since the G is -1, it means that the current flow direction should be opposite of what is shown in the picture and charge the capacitor Ci right?

By the way, do you have any idea why would we need to model the VCO with an integrator?

In a PLL, the VCO is modeled as an integrator because, well, the loop is phase locked. The inputs to the phase detector have to have units of phase (radians or degrees). A VCO has output units of phase/time (e.g, radians/sec). Phase is the integral of frequency, so the VCO's transfer function must be Ko/s in order to have output units of phase.

Did that make sense?

 

Well not exactly.
For example if we have VCVS with gain = Vin/Va = 10V/V
And we have a "control" voltage equal 1V and Rs=2K, and we want 10V across Rload resistor.
And now if we connect VCVS with input resistance low (compare to Rsource). We don't get 10V on the output becaues the load effect of our VCVS input resistance.

So the "equivalent" of a voltage gain is equal
Au = 3.33V/1V = 3.33V/V (but we want gain to be equal 10).

But if we chose R1>>Rsource

Surprisingly we get almost 10V across the load

That's a very clear illustration, thanks. Previously I mentioned

source resistance doesn't give a significant impact on the load voltage drop since its' resistance is small as compare to the load resistance.

Maybe I should rephrase the "source resistance" to "R1 resistance" referring to your diagram. If R1 is very large as compare to Rload, then we will get the desire voltage gain across the load.

Just out of my curiosity, did you draw all the diagrams or you got it from somewhere? It's nicely portrayed. And how did you paste it within the page? I tried and can't paste it like usual , I can just attach it.

 

In a PLL, the VCO is modeled as an integrator because, well, the loop is phase locked. The inputs to the phase detector have to have units of phase (radians or degrees). A VCO has output units of phase/time (e.g, radians/sec). Phase is the integral of frequency, so the VCO's transfer function must be Ko/s in order to have output units of phase.

Did that make sense?

Let me analyze what you have mentioned step by step:

The inputs to the phase detector have to have units of phase (radians or degrees)

The inputs to the phase detector are basically two sine or square waves which are out of phase (during out of lock). It's the phase detector that output the phase difference, contributing "phase unit", can I explain in this manner? Please correct me if I am wrong. Moreover, the phase detector also has a gain (2/∏ for XOR phase detector as can be seen in the attach).

Now let's get back to VCO modeling. Ok, I get the idea of phase/frequency output and the integration. Attached also the modeling illustration. But a VCO would just output a signal which frequency depends on input voltage, what's the different having a frequency or phase output? In the attachment, under the bullet Intuition of integral relationship between frequency and phase, there's a diagram of 2 waveforms. Do you have any idea what does it illustrates?

 

The VCO needs the output expressed in terms of phase because it feeds back to a phase detector whose transfer function is in terms of volts/radian, (or amps per radian, in case of a charge pump output). If the inputs to the phase detector are not in radians, then the math won't work when you do the analysis.
The drawing doesn't do much for me. Think of constant frequency being the equivalent of a ramp of phase (phase is linearly increasing with time). When the loop is locked, both ramps at the phase detector input have identical slopes. If the frequencies at the phase detector inputs are different, then the phase slopes are different, causing the output of the phase detector to increase or decrease, creating an error signal which should pull the VCO frequency toward lock.

 

Just out of my curiosity, did you draw all the diagrams or you got it from somewhere? It's nicely portrayed.

Yes, I drew these diagrams with help of Paint
http://forum.allaboutcircuits.com/showthread.php?p=335917#post335917

And how did you paste it within the page? I tried and can't paste it like usual , I can just attach it.

First I attach the picture next I use "Attachments" (paperclip)


Or Right-Click "Copy Image Location" and "Insert image"

 

The VCO needs the output expressed in terms of phase because it feeds back to a phase detector whose transfer function is in terms of volts/radian, (or amps per radian, in case of a charge pump output). If the inputs to the phase detector are not in radians, then the math won't work when you do the analysis.
The drawing doesn't do much for me. Think of constant frequency being the equivalent of a ramp of phase (phase is linearly increasing with time). When the loop is locked, both ramps at the phase detector input have identical slopes. If the frequencies at the phase detector inputs are different, then the phase slopes are different, causing the output of the phase detector to increase or decrease, creating an error signal which should pull the VCO frequency toward lock.

Thanks for the explanation. Yeah, the phase is a ramp because it's integration of frequency.