[Vol. 4 - Chp. 12 - Pg. 2] Typo in clock delay.

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Michael Spencer

Joined Dec 31, 1969
0
http://www.allaboutcircuits.com/vol_4/chpt_12/2.html

tS=100ns
tH=60ns
tP=200-400ns typ/max
tS is the setup time, the time data must be present before clock time. In this case data must be present at D 100ns prior to the clock. Furthermore, the data must be held for hold time tH=60ns after clock time. These two conditions must be met to reliably clock data from D to Q of the Flip-Flop.

There is no problem meeting the setup time of 60ns as the data at D has been there for the whole previous clock period if it comes from another shift register stage. For example, at a clock frequency of 1 Mhz, the clock period is 1000 µs, plenty of time. Data will actually be present for 1000µs prior to the clock, which is much greater than the minimum required tS of 60ns.
The last paragraph twice states that the setup time (tS) is 60ns, when above it says it is 100ns.
 

retched

Joined Dec 5, 2009
5,208
I believe its telling you that the minimum is 60ns, so the 100ns satisfies that.

[ed]
After reading the datasheet, I think you may be correct. Sorta. The datashees has 50ns an a minimum and 100ns as an average and 60ns for a minimum for hold time
[/ed]
 
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