I'm layout out flex FPC with an Atmel D20 Cortex 0 QFN mount, and it has a die pad (thermal pad).
Am I allowed or better is it normal, to run my traces under my chip using vias under the thermal pad like I would on a regular pin version of the chip? Seems like a risk of vias accidently shorting on the die pad, but I can't find anything say do or don't do.
I read that people put Via's to help disappate the heat, but I'm not asking that about that.
Thanks for the help.
Brent
Am I allowed or better is it normal, to run my traces under my chip using vias under the thermal pad like I would on a regular pin version of the chip? Seems like a risk of vias accidently shorting on the die pad, but I can't find anything say do or don't do.
I read that people put Via's to help disappate the heat, but I'm not asking that about that.
Thanks for the help.
Brent