VHDL

Discussion in 'Programmer's Corner' started by Amadan, Oct 28, 2005.

  1. Amadan

    Thread Starter New Member

    Oct 28, 2005
    1
    0
    I'm trying to design a rolling average filter that involves a data generator, a filter and a display (7 segment) some switches and a 50Mhz clock which i need to change it to 1Hz.
    Any ideas?
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Hi,

    You can always divide the 50 mHz down, but, unless there's some requirement to use the higher frequency, it will be cheaper and use less board space to get a cmos oscillator to generate the 1 kHz frequency.
     
  3. Dave

    Retired Moderator

    Nov 17, 2003
    6,960
    144
    The way I usually implement this is to create a counter within a process in VHDL. However, I've never tried generating a 1Hz signal form a 50MHz clock, so don't know how well your device will implement the design.

    Code ( (Unknown Language)):
    1. process(clk)
    2.         begin
    3.  
    4.                 if counter = "<max_divisor>"      
    5.                 then
    6.                         counter <= "0000";
    7.                         else if clk = '1' and clk'event
    8.                         then
    9.                                 counter <= counter + 1;
    10.                         end if;
    11.                 end if;
    12.  
    13.         end process;
    14.  
    15. process(clk)
    16.         begin
    17.         
    18.                 if clk = '1' and clk'event
    19.                 then
    20.                         if counter = "0000"
    21.                         then
    22.                                 newCLK <= NOT newCLKp;
    23.                         end if;        
    24.                 end if;
    25.                         
    26.         end process;
    You may also need to latch the output depending on your requirements.

    This design has worked well for generating different clocking rates for implementing display drivers on FPGAs.

    However, beenthere's idea is a worthwhile consideration.
     
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