vhdl/verilog code for interfacing DDR# SDRAM to vertex6 or spartran6 fpga

Discussion in 'General Electronics Chat' started by ideas, Mar 26, 2012.

  1. ideas

    Thread Starter New Member

    Mar 16, 2012
    7
    0
    hi
    can any1 plz help me in writing a vhdl/verilog code for interfacing DDR3 SDRAM to vertex6 or spartran6 fpga.
    Thank you.
     
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