VHDL Timing Question

Discussion in 'Homework Help' started by Digit0001, Jun 11, 2010.

  1. Digit0001

    Thread Starter Member

    Mar 28, 2010
    89
    0
    Hi
    Can someone tell me if this is correct?
    Assume that the following are concurrent VHDL statements:
    a) L <= P nand Q after 10ns;
    b) M <= L nor N after 5ns;
    c) R <= not M;

    Initially at time t=0ns, P=1, Q=1 and N=0. If Q becomes 0 at time t=4ns
    1)At what time will statement (a) execute?
    10ns later
    2) At what time will L be updated?
    14ns
    3) At what time will statement (c) execute?
    5ns
    4) At what time will R be updated?
    19ns

    P.S
     
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