VHDL Timescale

Discussion in 'Programmer's Corner' started by visu9522, Apr 16, 2014.

  1. visu9522

    Thread Starter New Member

    Apr 16, 2014
    2
    0
    Hi Forum,

    Does VHDL have timescale specification like verilog?if yes what is the syntax for that?
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    No, not that I'm aware of.

    The simulation timescale is set in the simulator.

    I never understood why Verilog included it...:confused:
     
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