Hi Guys,
I have just started learning about VHDL and I need to know the basics so Ive been reading loads but I cant seem to get any information on what a VHDL Testbench is or its advantages. Can anyone just explain what it is so I can at the very least get some sort of idea of how it works?
Cheers
J
I have just started learning about VHDL and I need to know the basics so Ive been reading loads but I cant seem to get any information on what a VHDL Testbench is or its advantages. Can anyone just explain what it is so I can at the very least get some sort of idea of how it works?
Cheers
J