hi all,
can any one please tel me what this perticular statement in the code means...

pre1<=conv_std_logic_vector(mul1,8)

per1 is a signal and mul1 is also a signal....

awaiting reply

 

conv_std_logic_vector converts integers (signed, unsigned and std_ulogic) into type std_logic_vector. It is a part of the std_logic_arith library provided in VHDL to define and perform some basic arithmetic operations on common digital data-types.

The std_logic_vector type is used for arrays of std_logic types. And std_logic types are resolved versions of std_ulogic which can have any of the following states:

- 'U': uninitialized.
- 'X': unknown
- '0': logic 0
- '1': logic 1
- 'Z': High Impedance
- 'W': Weak signal, can't tell if it should be 0 or 1
- 'L': Weak signal that should probably go to 0
- 'H': Weak signal that should probably go to 1
- '-': Don't care

Dave

 

This function basically convert (called conversion function) an integer/signed/unsigned/std_ulogic type to std_logic_vector of size 8.

The function definitions are in IEEE.std_logic_arith as pointed by Dave:

function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;


A sample function implementation is:

function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
begin
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
end;