helo ,
I designed a couple of circuits and I want to combine them,
but before I do that, I'm doing a real hardware test for each...
my first was a motor and it finally works
I am now trying to make the communication of the design to work
this is the only design I just wrote the code and didn't draw it on word mostly because it's only the rx side of it and i am having troubled on figuring how it's supposed to be
I am getting warnings about stuck output pins (the leds) into ground
any help or insight will be greatly appreciate
Rich (BB code):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift_reg is
generic (
Baud_Rate: time:= 104 us;
clock_period: time:= 20 ns
);
port ( Rst: in std_logic;
Clk: in std_logic;
Enable: in std_logic;
Rx: in std_logic;
Led: out std_logic_vector (9 downto 0);
busy: out std_logic
);
attribute altera_chip_pin_lc: string;
attribute altera_chip_pin_lc of Clk : signal is "@N2";
attribute altera_chip_pin_lc of Rst : signal is "@G26";
attribute altera_chip_pin_lc of Led : signal is "@AD24, @AC23, @AC21, @AD21, @AD23, @AD22, @AC22, @AB21, @AF23, @AE23";
attribute altera_chip_pin_lc of Enable: signal is "@N25";
attribute altera_chip_pin_lc of busy: signal is "@J22";
attribute altera_chip_pin_lc of Rx: signal is "@D25";
end entity shift_reg;
architecture arc_shift_reg of shift_reg is
signal Parallel_Data_In: std_logic_vector (9 downto 0);
signal counter: std_logic_vector (7 downto 0);
signal freq_counter: unsigned (12 downto 0);
constant com_baud_rate: integer := Baud_Rate/clock_period;
-- signal parallel_Data_Out: std_logic_vector (7 downto 0);
begin
serial_shift_reg: process(Clk,Rst)
begin
if (Rst = '0') then
parallel_Data_In <= (others => '0');
freq_counter <= (others => '0');
counter <= (others => '0');
Led <= (others => '0');
busy <= '0';
elsif rising_edge(Clk) then
if (Enable = '1') and (freq_counter = com_baud_rate) then
freq_counter <= (others => '0');
counter <= counter + 1;
Parallel_Data_In(9) <= Rx;
Parallel_Data_In(8) <= Parallel_Data_In(9);
Parallel_Data_In(7) <= Parallel_Data_In(8);
Parallel_Data_In(6) <= Parallel_Data_In(7);
Parallel_Data_In(5) <= Parallel_Data_In(6);
Parallel_Data_In(4) <= Parallel_Data_In(5);
Parallel_Data_In(3) <= Parallel_Data_In(4);
Parallel_Data_In(2) <= Parallel_Data_In(3);
Parallel_Data_In(1) <= Parallel_Data_In(2);
Parallel_Data_In(0) <= Parallel_Data_In(1);
else
freq_counter <= freq_counter + 1;
end if;
if (counter = 10) and (Parallel_Data_In(0) = '1') and (Parallel_Data_In(0) = '0') then
--Parallel_Data_Out <= parallel_Data_In;
Led <= parallel_Data_In;
counter <= (others => '0');
elsif ( counter = 10) then
counter <= (others => '0');
else
busy <= '1';
end if;
end if;
end process;
end architecture arc_shift_reg;
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