Vhdl shift register for RxD

Discussion in 'Programmer's Corner' started by rotemkim, Feb 16, 2011.

  1. rotemkim

    Thread Starter New Member

    Jan 19, 2011
    3
    0
    helo ,

    I designed a couple of circuits and I want to combine them,
    but before I do that, I'm doing a real hardware test for each...
    my first was a motor and it finally works
    I am now trying to make the communication of the design to work
    this is the only design I just wrote the code and didn't draw it on word mostly because it's only the rx side of it and i am having troubled on figuring how it's supposed to be
    I am getting warnings about stuck output pins (the leds) into ground
    any help or insight will be greatly appreciate
    Code ( (Unknown Language)):
    1.  
    2. library ieee;
    3. use ieee.std_logic_1164.all;
    4. use ieee.std_logic_arith.all;
    5. use ieee.std_logic_unsigned.all;
    6.  
    7. entity shift_reg  is
    8. generic (
    9.   Baud_Rate: time:= 104 us;
    10.   clock_period: time:= 20 ns
    11.   );
    12. port ( Rst: in std_logic;
    13.    Clk: in std_logic;
    14.    Enable: in std_logic;
    15.    Rx: in std_logic;
    16.    Led: out std_logic_vector (9 downto 0);
    17.    busy: out std_logic
    18.   );
    19.   attribute altera_chip_pin_lc: string;
    20.   attribute altera_chip_pin_lc of Clk  : signal is "@N2";
    21.   attribute altera_chip_pin_lc of Rst : signal is "@G26";
    22.   attribute altera_chip_pin_lc of Led  : signal is "@AD24, @AC23, @AC21, @AD21, @AD23, @AD22, @AC22, @AB21, @AF23, @AE23";
    23.   attribute altera_chip_pin_lc of Enable: signal is "@N25";
    24.   attribute altera_chip_pin_lc of busy: signal is "@J22";
    25.   attribute altera_chip_pin_lc of Rx: signal is "@D25";
    26. end entity shift_reg;
    27. architecture arc_shift_reg of shift_reg is
    28.  signal Parallel_Data_In: std_logic_vector (9 downto 0);
    29.  signal counter: std_logic_vector (7 downto 0);
    30.  signal freq_counter: unsigned (12 downto 0);
    31.  constant com_baud_rate: integer := Baud_Rate/clock_period;
    32. -- signal parallel_Data_Out: std_logic_vector (7 downto 0);
    33. begin
    34.  
    35. serial_shift_reg: process(Clk,Rst)
    36.      begin
    37.       if (Rst = '0') then
    38.        parallel_Data_In <= (others => '0');
    39.        freq_counter <= (others => '0');
    40.        counter <= (others => '0');
    41.        Led <= (others => '0');
    42.        busy <= '0';
    43.       elsif rising_edge(Clk) then
    44.        if (Enable = '1') and (freq_counter = com_baud_rate) then
    45.         freq_counter <= (others => '0');
    46.         counter <= counter + 1;
    47.         Parallel_Data_In(9) <= Rx;
    48.         Parallel_Data_In(8) <= Parallel_Data_In(9);
    49.         Parallel_Data_In(7) <= Parallel_Data_In(8);
    50.         Parallel_Data_In(6) <= Parallel_Data_In(7);
    51.         Parallel_Data_In(5) <= Parallel_Data_In(6);
    52.         Parallel_Data_In(4) <= Parallel_Data_In(5);
    53.         Parallel_Data_In(3) <= Parallel_Data_In(4);
    54.         Parallel_Data_In(2) <= Parallel_Data_In(3);
    55.         Parallel_Data_In(1) <= Parallel_Data_In(2);
    56.         Parallel_Data_In(0) <= Parallel_Data_In(1);
    57.        else
    58.         freq_counter <= freq_counter + 1;
    59.        end if;
    60.        if (counter = 10) and (Parallel_Data_In(0) = '1') and (Parallel_Data_In(0) = '0') then
    61.         --Parallel_Data_Out <= parallel_Data_In;
    62.         Led <= parallel_Data_In;
    63.         counter <= (others => '0');
    64.        elsif ( counter = 10) then
    65.         counter <= (others => '0');
    66.        else
    67.         busy <= '1';
    68.        end if;
    69.       end if;
    70.     end process;
    71. end architecture arc_shift_reg;
     
  2. rotemkim

    Thread Starter New Member

    Jan 19, 2011
    3
    0
    the warning is fixed thanks
    anybody reading this ?
     
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