VHDL question

Discussion in 'Programmer's Corner' started by hby, Dec 7, 2013.

  1. hby

    Thread Starter New Member

    Dec 7, 2013
    1
    0
    Hey guys. I'm new to this forum and new to VHDL. I'm trying to create a simple remote control with three inputs Nex, Prev and Number and two outputs
    Channel (0-9)which has the same value as Number and Video which is asserted when Number is "0000". The code that I've written compiles that problem is that it's not giving me a right answer. Please can someone help me find the error in my logic?

    code:
    Code ( (Unknown Language)):
    1.  
    2. library ieee;
    3. use ieee.std_logic_1164.all;
    4. use ieee.std_logic_arith.all;
    5. use ieee.std_logic_unsigned.all;
    6.  
    7. entity remote is
    8.   port( nex,clock,prev: in std_logic;
    9.         number: in std_logic_vector(3 downto 0);
    10.         video: out std_logic;
    11.         channel: out std_logic_vector(3 downto 0));
    12. end entity;
    13.  
    14. architecture arch of remote is
    15.   signal chan:std_logic_vector (3 downto 0):=(others=>'0');
    16.   signal vid:std_logic;
    17.   type state is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
    18.   signal current_state, next_state: state:=S0;
    19.   begin
    20.     process(nex,prev,number)
    21.       begin
    22.         if(nex='1' or prev='1') then
    23.     case current_state is
    24.     when S0=>
    25.       if(nex='1' and prev='0')
    26.       then  next_state<=S1;
    27.             vid<='0';
    28.             chan<="0001";
    29.       elsif(nex='0' and prev='1')
    30.       then  next_state<=S9;
    31.             vid<='0';
    32.             chan<="1001";
    33.       elsif(nex='1' and prev='1')
    34.       then  next_state<=S0;
    35.             vid<='1';
    36.             chan<="0000";
    37.     end if;
    38.    
    39.     when S1=>
    40.       if(nex='1' and prev='0')
    41.       then  next_state<=S2;
    42.             vid<='0';
    43.             chan<="0010";
    44.       elsif(nex='0' and prev='1')
    45.       then  next_state<=S0;
    46.             vid<='1';
    47.             chan<="0000";
    48.       elsif(nex='1' and prev='1')
    49.       then  next_state<=S1;
    50.             vid<='0';
    51.             chan<="0001";
    52.     end if;
    53.    
    54.     when S2=>
    55.       if(nex='1' and prev='0')
    56.       then  next_state<=S3;
    57.             vid<='0';
    58.             chan<="0011";
    59.       elsif(nex='0' and prev='1')
    60.       then  next_state<=S1;
    61.             vid<='0';
    62.             chan<="0001";
    63.       elsif(nex='1' and prev='1')
    64.       then  next_state<=S2;
    65.             vid<='0';
    66.             chan<="0010";
    67.     end if;
    68.    
    69.     when S3=>
    70.       if(nex='1' and prev='1')
    71.       then  next_state<=S4;
    72.             vid<='0';
    73.             chan<="0100";
    74.       elsif(nex='0' and prev='1')
    75.       then  next_state<=S2;
    76.             vid<='0';
    77.             chan<="0010";
    78.       elsif(nex='1' and prev='1')
    79.       then  next_state<=S3;
    80.             vid<='0';
    81.             chan<="0011";
    82.     end if;
    83.    
    84.     when S4=>
    85.       if(nex='1' and prev='0')
    86.       then  next_state<=S5;
    87.             vid<='0';
    88.             chan<="0101";
    89.       elsif(nex='0' and prev='1')
    90.       then  next_state<=S3;
    91.             vid<='0';
    92.             chan<="0011";
    93.       elsif(nex='1' and prev='1')
    94.       then  next_state<=S4;
    95.             vid<='0';
    96.             chan<="0100";
    97.     end if;
    98.    
    99.     when S5=>
    100.       if(nex='1' and prev='0')
    101.       then  next_state<=S6;
    102.             vid<='0';
    103.             chan<="0110";
    104.       elsif(nex='0' and prev='1')
    105.       then  next_state<=S4;
    106.             vid<='0';
    107.             chan<="0100";
    108.       elsif(nex='1' and prev='1')
    109.       then  next_state<=S5;
    110.             vid<='0';
    111.             chan<="0101";
    112.     end if;
    113.    
    114.     when S6=>
    115.       if(nex='1' and prev='0')
    116.       then  next_state<=S7;
    117.             vid<='0';
    118.             chan<="0111";
    119.       elsif(nex='0' and prev='1')
    120.       then  next_state<=S5;
    121.             vid<='0';
    122.             chan<="0101";
    123.       elsif(nex='1' and prev='1')
    124.       then  next_state<=S6;
    125.             vid<='0';
    126.             chan<="0110";
    127.     end if;
    128.    
    129.     when S7=>
    130.       if(nex='1' and prev='0')
    131.       then  next_state<=S8;
    132.             vid<='0';
    133.             chan<="1000";
    134.       elsif(nex='0' and prev='1')
    135.       then  next_state<=S6;
    136.             vid<='0';
    137.             chan<="0110";
    138.       elsif(nex='1' and prev='1')
    139.       then  next_state<=S7;
    140.             vid<='0';
    141.             chan<="0111";
    142.     end if;
    143.    
    144.     when S8=>
    145.       if(nex='1' and prev='0')
    146.       then  next_state<=S9;
    147.             vid<='0';
    148.             chan<="1001";
    149.       elsif(nex='0' and prev='1')
    150.       then  next_state<=S7;
    151.             vid<='0';
    152.             chan<="0111";
    153.       elsif(nex='1' and prev='1')
    154.       then  next_state<=S8;
    155.             vid<='0';
    156.             chan<="1000";
    157.     end if;
    158.    
    159.     when S9=>
    160.       if(nex='1' and prev='0')
    161.       then  next_state<=S0;
    162.             vid<='1';
    163.             chan<="0000";
    164.       elsif(nex='0' and prev='1')
    165.       then  next_state<=S8;
    166.             vid<='0';
    167.             chan<="1000";
    168.       elsif(nex='1' and prev='1')
    169.       then  next_state<=S9;
    170.             vid<='0';
    171.             chan<="1001";
    172.     end if;
    173. end case;
    174. else
    175.   case number is
    176.    
    177.     when "0000"=>
    178.       next_state<=S0;
    179.       vid<='1';
    180.       chan<="0000";
    181.    
    182.     when "0001"=>
    183.       next_state<=S1;
    184.       vid<='0';
    185.       chan<="0001";
    186.    
    187.     when "0010"=>
    188.       next_state<=S2;
    189.       vid<='0';
    190.       chan<="0010";
    191.  
    192.     when "0011"=>
    193.       next_state<=S3;
    194.       vid<='0';
    195.       chan<="0011";
    196.  
    197.     when "0100"=>
    198.       next_state<=S4;
    199.       vid<='0';
    200.       chan<="0100";
    201.  
    202.     when "0101"=>
    203.       next_state<=S5;
    204.       vid<='0';
    205.       chan<="0101";
    206.  
    207.     when "0110"=>
    208.       next_state<=S6;
    209.       vid<='0';
    210.       chan<="0110";
    211.  
    212.     when "0111"=>
    213.       next_state<=S7;
    214.       vid<='0';
    215.       chan<="0111";
    216.  
    217.     when "1000"=>
    218.       next_state<=S8;
    219.       vid<='0';
    220.       chan<="1000";
    221.      
    222.     when "1001"=>
    223.       next_state<=S9;
    224.       vid<='0';
    225.       chan<="1001";
    226.     when others=>
    227.       next_state<=S0;
    228.       vid<='1';
    229.       chan<="0000";
    230.      
    231.      
    232.       end case;
    233. end if;
    234.  
    235. end process;
    236.  
    237. SEQ: process(clock)
    238. begin
    239. if clock'event and clock = '1' then
    240. current_state <= next_state;
    241. video<=vid;
    242. channel<=chan;
    243. end if;
    244. end process SEQ;
    245.  
    246. end arch;
    247.  
    248. test bench:
    249.  
    250. library ieee;
    251. use ieee.std_logic_1164.all;
    252. use ieee.std_logic_arith.all;
    253. use ieee.std_logic_unsigned.all;
    254.  
    255. entity testbench is
    256. end testbench;
    257.  
    258. architecture testbench of testbench is
    259.  
    260. component remote port(nex,clock,prev: in std_logic;
    261.         number: in std_logic_vector(3 downto 0);
    262.         video: out std_logic;
    263.         channel: out std_logic_vector(3 downto 0));
    264. end component;
    265.  
    266. signal nex : std_logic := '0';
    267. signal prev : std_logic := '0';
    268. signal clock : std_logic := '0';
    269. signal number : std_logic_vector(3 downto 0) := "0000";
    270. signal video : std_logic;
    271. signal channel : std_logic_vector(3 downto 0);
    272.  
    273. begin
    274.  
    275.   UUT: remote port map (nex => nex, prev => prev, clock => clock, number => number, video => video, channel => channel);
    276.     process
    277.       begin
    278.         Clock <= '0' ; wait for 20 ns;
    279.         Clock <= '1' ; wait for 20 ns;
    280.     end process;
    281.    
    282.     process
    283.       begin
    284.        
    285.         number <= "0110"; nex <= '1'; prev <= '0'; wait for 30 ns;
    286.         number <= "0110"; nex <= '0'; prev <= '1'; wait for 230 ns;
    287.     end process;
    288. end testbench;
    289.  
     
    Last edited by a moderator: Dec 7, 2013
  2. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    It appears that you logic isn't looking at "number" only "nxt" "prev" and "state". This is becase in your testbench, either nxt or prev is '1'. I would need to know more about what you're trying to accomplish and what is the definition if "right" and "wrong" answers is to help more. Provide more details.
     
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