VHDL question

Discussion in 'Programmer's Corner' started by modukuri, May 17, 2004.

  1. modukuri

    Thread Starter New Member

    May 17, 2004
    1
    0
    Hi:

    I need to compare the simulation results from VHDL to verify my design. To accomplish that, I'm trying to use VHDL file declarations to input the data and to write the output data back into a file. My input file is in the form of a matrix (data type is integer). I'm doing the following to read the data values from the input file into an array.

    type file1 is of integer;
    file data_in : file1 is in "input.txt";

    Then in the process,I have the follwing:

    for i in row'range loop
    for j in column'range loop
    while not endfile(data_in) loop
    read(data_in, data(i,j));
    end loop;
    .....etc

    data... is defined as an array.

    The code is being complied without any errors.But, when simulated, the signal corresponding to the"data" is not updated.

    I would appreciate,if somebody can help me out with this or any suggetions regarding ,(reading the data from file into an array) are most welcome.

    Thanks,
    Modukuri
     
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