I am trying to create a logical expression for this circuit. I have designed the circuit in Quartus, but I am having problems figuring out the logical expression so I can build the VHDL program. The inverter is what's confusing me. I came up with A'B + A'CD + B as the output, but I wasn't sure if I should invert the output?

 

I am trying to create a logical expression for this circuit. I have designed the circuit in Quartus, but I am having problems figuring out the logical expression so I can build the VHDL program. The inverter is what's confusing me. I came up with A'B + A'CD + B as the output, but I wasn't sure if I should invert the output?

I am not entirely sure why you need a Booolean expression to build a VHDL configuration (there is no programming in VHDL).

Beyond that, write out a truth table and determine what the output of the circuit would be for all possible input values.

You can also do it by writing the Boolean expression at each point in the circuit. That way, you can identify the progression of the logic.

 

I was able to figure it out, thanks.

X = A + B'C' + B'D'

entity AND_OR is
port (A,B,C,D: in bit; X: out bit);
end entity AND_OR;
architecture LogicFunction of AND_OR is
begin
X <= (A) or (not B and not C) or (not B and not D);
end architecture LogicFunction;

 

I don't think you have the transfer function correct.

According to your diagram:

out = !(!a&b or !a&c&d or d&b&!d)

Now, there is a very easy simplification for the 3rd term. You can apply the distro property and De Morgan's theorem to the rest.