VHDL prob

Discussion in 'Programmer's Corner' started by PwrOverload, Aug 23, 2008.

  1. PwrOverload

    Thread Starter New Member

    Aug 19, 2008
    5
    0
    I keep getting this error in my VHDL program:
    "Error (10515): VHDL type mismatch error at ALU.vhd(42): std_ulogic type does not match string literal"

    My code is:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity ALU is
    port (A,B : in std_logic_vector(7 downto 0);
    S: in std_logic_vector(3 downto 0);
    Cin: in std_logic;
    F: out std_logic_vector(7 downto 0);
    Cout: out std_logic);
    end ALU;
    architecture struct of ALU is
    signal sCout,sCOUTe: std_logic;
    signal sF,sFe: std_logic_vector(7 downto 0);
    component EIGHTBITADD
    port (A,B : in std_logic_vector(7 downto 0);
    CIN : in std_logic;
    S: in std_logic_vector(2 downto 0);
    F: out std_logic_vector(7 downto 0);
    COUT : out std_logic);
    end component;
    component SHIFT_ROTATE
    port (A,B: in std_logic_vector(7 downto 0);
    S: in std_logic_vector(2 downto 0);
    Cin: in std_logic;
    F: out std_logic_vector(7 downto 0);
    Cout: out std_logic);
    end component;
    begin
    u1: EIGHTBITADD port map(A,B,Cin,S(2 downto 0),sFe,sCOUTe);
    u2: SHIFT_ROTATE port map(A,B,S(2 downto 0),Cin,sF,sCout);
    MX_ALU: process(S(3),A,B)
    begin
    case S(3) is
    when "0" => F <= sFe; Cout <= sCOUTe; <-- error occurs here
    when "1" => F <= sF; Cout <= sCout; <-- error occurs here
    when others => F <= X"00"; Cout <= '1';
    end case;
    end process;
    end struct;

    any help would be appreciated.
     
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