VHDL -Please check my code

Discussion in 'Programmer's Corner' started by payel, May 26, 2015.

  1. payel

    Thread Starter New Member

    Feb 10, 2015
    5
    0
    Code (Text):
    1. ----------------------------------------------------------------------------------
    2. -- Company:
    3. -- Engineer:
    4. --
    5. -- Create Date:    14:30:01 05/25/2015
    6. -- Design Name:
    7. -- Module Name:    count - Behavioral
    8. -- Project Name:
    9. -- Target Devices:
    10. -- Tool versions:
    11. -- Description:
    12. --
    13. -- Dependencies:
    14. --
    15. -- Revision:
    16. -- Revision 0.01 - File Created
    17. -- Additional Comments:
    18. --
    19. ----------------------------------------------------------------------------------
    20. library IEEE;
    21. use IEEE.STD_LOGIC_1164.ALL;
    22. use IEEE.STD_LOGIC_ARITH.ALL;
    23. use IEEE.STD_LOGIC_UNSIGNED.ALL;
    24.  
    25. ---- Uncomment the following library declaration if instantiating
    26. ---- any Xilinx primitives in this code.
    27. --library UNISIM;
    28. --use UNISIM.VComponents.all;
    29.  
    30. entity count is
    31.     Port ( count  : in  STD_LOGIC_vector (1 downto 0);
    32.            reset  : in  STD_LOGIC ;
    33.            output : out  STD_LOGIC_vector (1 downto 0);
    34.              clk : in  STD_LOGIC);
    35. end count;
    36.  
    37. architecture Behavioral of count is
    38.  
    39. signal y:STD_LOGIC_vector (1 downto 0);
    40.  
    41. begin
    42. process ( reset , clk)
    43.  
    44. variable var: integer := 100;
    45. begin
    46.  
    47.  
    48. y <= count ;
    49.  
    50.  
    51. l1: loop
    52. exit l1 when var = 0 ;
    53.  
    54. if (reset='0') then
    55. if (rising_edge(clk)) then
    56.  
    57.  
    58. y <= y+"01";
    59. var := var-1;
    60.  
    61. else
    62.  
    63. end if ;
    64.  
    65. output (1 downto 0) <= y (1 downto 0);
    66.  
    67.  
    68.  
    69. else
    70. output (1 downto 0)<="00";
    71. end if;
    72.  
    73. end loop;
    74.  
    75.  
    76. end process;
    77. end Behavioral;


    is my program ok. plz someone ckeck , it is showing no syntax error however , but plz point the logicasl error if any . thank you.
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    How should we know? You didn´t provide any specification of what the code si supposed to do.
     
  3. payel

    Thread Starter New Member

    Feb 10, 2015
    5
    0
    Code (Text):
    1. ----------------------------------------------------------------------------------
    2. -- Company:
    3. -- Engineer:
    4. --
    5. -- Create Date:    14:30:01 05/25/2015
    6. -- Design Name:
    7. -- Module Name:    count - Behavioral
    8. -- Project Name:
    9. -- Target Devices:
    10. -- Tool versions:
    11. -- Description:
    12. --
    13. -- Dependencies:
    14. --
    15. -- Revision:
    16. -- Revision 0.01 - File Created
    17. -- Additional Comments:
    18. --
    19. ----------------------------------------------------------------------------------
    20. library IEEE;
    21. use IEEE.STD_LOGIC_1164.ALL;
    22. use IEEE.STD_LOGIC_ARITH.ALL;
    23. use IEEE.STD_LOGIC_UNSIGNED.ALL;
    24.  
    25. ---- Uncomment the following library declaration if instantiating
    26. ---- any Xilinx primitives in this code.
    27. --library UNISIM;
    28. --use UNISIM.VComponents.all;
    29.  
    30. entity count is
    31.     Port (
    32.             reset  : in  STD_LOGIC ;
    33.            output : out  STD_LOGIC_vector (1 downto 0);
    34.               clk : in  STD_LOGIC);
    35. end count;
    36.  
    37. architecture Behavioral of count is
    38.  
    39. begin
    40. process ( reset , clk)
    41.  
    42. variable y:STD_LOGIC_vector (1 downto 0):= "00";
    43.  
    44.  
    45. begin
    46.  
    47.  
    48. if (reset='0') then
    49. if (rising_edge(clk)) then
    50.  
    51.  
    52. y := y+"01";
    53.  
    54.  
    55. else
    56.  
    57. end if ;
    58.  
    59. output (1 downto 0) <= y (1 downto 0);
    60.  
    61.  
    62.  
    63. else
    64. output (1 downto 0)<="00";
    65. end if;
    66.  
    67.  
    68.  
    69.  
    70. end process;
    71. end Behavioral;
    72.  
    73.  
    74.  
    75.  
    76.  
    check this , ignore the above program.


    o, ok sorry it is a 2 bit counter . where the initial value is provided "00" and then it will count 01, 10, 11 ,00 but b4 every count it will check reset and clk.
     
  4. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    I have to say I used VHDL a long time ago, so I can´t really tell if the syntax is correct. Nevertheless the code looks correct, even though all the (1 downto 0) seem superfluous and not really needed. How did the simulation come out?

    Also, you should start your own thread, not resurrect this 10 years dead thread.
     
  5. payel

    Thread Starter New Member

    Feb 10, 2015
    5
    0
    if i simply want to design a clock with a time period of some delay as given for each on and off period . then will my following code work.

    Code (Text):
    1. begin
    2. process
    3. begin
    4.  
    5. a <= '1';
    6.  
    7.  
    8.  
    9. var := 5000;
    10. while var >0 loop
    11. var := var-1;
    12. end loop;
    13.  
    14.  
    15. a <= '0';
    16.  
    17.  
    18.  
    19. var := 5000;
    20. while var >0 loop
    21. var := var-1;
    22. end loop;
    23.  
    24.  
    25. end process ;
     
  6. payel

    Thread Starter New Member

    Feb 10, 2015
    5
    0


    ok, 1stly the syntax is correct , i have compiled it . i want to know if there is any logical error bec i often confuse it with c /fortran. and another thing , plz say me how to start a new thread .
     
  7. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    Go to http://forum.allaboutcircuits.com/forums/programmers-corner.12/ click Start new thread in the upper right corner, and please make sure to give the thread a good title that describes it for others. Something like VHDL counter should be ok.

    Why do you think that code will produce 10ns clock? It could be be 10000 seconds period just as well. Or maybe nothing at all if you try to synthesize it.
    If it is for simulation, why not try some wait statements or whatever its called in vhdl, instead of counting some illdefined iterations?
     
  8. payel

    Thread Starter New Member

    Feb 10, 2015
    5
    0





    yes actually i have read process statement . there i have read that if the process has sensitivity list then signal assignment occurs only when all the statements of the process get executed . but if it has no ensitivity list then we need to give a wait statement after every signal assignment . but wait is not synthesizable. then what do we need to do or give in place of wait statement .


    say for eg:


    here a is firstly assigned with '1' and thenm with '0' . but wait statement is not synthesizable , so in place of wait what do i need to give so that firstly '1' is sent to a port c of fpga and then '0' is sent to the same port of fpga . can we use a delay in place of wait . for eg:


     
  9. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    In synthesis you cannot generate something from nothing. Your chip will need a clock input coming from an external oscillator, then you base everything on that clock.
     
  10. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Not all implementations of the wait statement are synthesizable, though there are that can be.
    A common way to do this is a process that is sensitive to clk and reset:
    Code (Text):
    1.  
    2. --entity declaration
    3.  
    4. architecture behavioral of <entity_name> is
    5.   signal internal_count : std_logic_vector (1 downto 0) := "00";
    6. begin
    7.  
    8.   --these are the same size, no need to specify their lengths
    9.   output <= internal_count;
    10.  
    11.   counter_proc: process (clk, reset)
    12.   begin
    13.     if (reset = '1') then
    14.       --reset state
    15.     elsif (rising_edge (clk)) then
    16.       --increment count
    17.     end if;
    18.   end process;
    19. end architecture;
    A synthesizable wait statement uses slightly different syntax:
    Code (Text):
    1.  
    2. --entity declaration
    3.  
    4. architecture behavioral of <entity_name> is
    5.   signal internal_count : std_logic_vector (1 downto 0) := "00";
    6. begin
    7.  
    8.   --these are the same size, no need to specify their lengths
    9.   output <= internal_count;
    10.  
    11.   counter_proc: process
    12.   begin
    13.     wait until clk='1' and clk'event;
    14.     if (reset = '0') then
    15.       --reset state
    16.     else
    17.       --increment count
    18.     end if;
    19.   end process;
    20. end architecture;
    This makes a synchronous reset however.

    To make an asynchronous reset, you could do something more like:
    Code (Text):
    1.  
    2. --entity declaration
    3.  
    4. architecture behavioral of <entity_name> is
    5.   signal internal_count : std_logic_vector (1 downto 0) := "00";
    6. begin
    7.  
    8.   --these are the same size, no need to specify their lengths
    9.   output <= internal_count when reset = '1' else " 00";
    10.  
    11.   counter_proc: process
    12.   begin
    13.     wait until clk='1' and clk'event;
    14.     --internal_count <= incremented value;
    15.   end process;
    16. end architecture;
    Hopefully this captures the idea without giving away too much.....

    The "wait for" form is not synthesizable, at least, not generally, though there may be synthesis tools that will, knowing what frequency a master clock is at, inner the logic required to generate those timings in the wait statements, though I wouldn't count on these existing.

    The 'wait for' is usually used in testbench writing to verify a synthesizable design before going into any hardware.
     
    Last edited: May 27, 2015
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