VHDL Logic

Discussion in 'General Electronics Chat' started by Dritech, May 26, 2015.

  1. Dritech

    Thread Starter Well-Known Member

    Sep 21, 2011
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    5
    Hi all,

    I am new to VHDL. Can someone please explain what is the difference between std_logic and std_logic_vactor ?
     
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    std_logic describes a single, 9-valued signal taking any value of: '0', '1', 'Z', 'X', 'W', 'H', 'L', '-', and 'Z'.

    The std_logic_vector is a bus, or group of std_logic signals.
     
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  3. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    When using std_logic_vector, one specifies the number of signals grouped into a bus using indicies in the signal declaration, ie;_

    std_logic_vector [31 downto 0] my_signal;
     
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