Dear guys,

I need some help programming VHDL.

I need to break up a 8bit binary data to 2 4-bit data. Below is a glimpse of the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
use work.CharLoopController.all;


entity Sub_prog_test is
Port ( en,reset,DisplayData,clk : in STD_LOGIC;
Data: in STD_LOGIC_VECTOR (7 downto 0);
);
end Sub_prog_test;

architecture Behavioral of Sub_prog_test is

begin

process (clk,en,reset)

variable upper_4bit, lower_4bit: std_logic_vector (3 downto 0);

--------------------Some statement-------------------------
.....................

upper_4bit<=Data(7)& Data(6)& Data(5)& Data(4);
lower_4bit<=Data(3)& Data(2)& Data(1)& Data(0);

However, when i do this, i get an error: "Wrong index type for Data."

Please help

Ridwan

 

Hi guys..

Realised my own mistake. Accidently named 2 variables similarly: 1 is data, other is Data. After changing Data to a new name: DataVar, everything went ok.

Shucks.. I thought VHDL syntax was case sensitive.

Best Regards

Ridwan

 

Hi,

i am a final year engineering student and i am seeking your help. I am required to design a Mesh Fabric Reference Design using VHDL programming.

please refer to the following document.

http://www.xilinx.com/support/documentation/application_notes/xapp698.pdf

sample source code is not available for this and i have to design this from scratch. Would you be willing to help me. There will be good incentives. Please reply if interested. Thanks.

 

Oh man, this game is pretty sweet. Why can't more games have cutscenes that you want to see more of?

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