VHDL: Help with FSM

Discussion in 'Programmer's Corner' started by goranbm, Mar 10, 2009.

  1. goranbm

    Thread Starter New Member

    Mar 10, 2009
    1
    0
    hello, I need help with my code.... I have made a code for input numbers from ps2 keyboard, and i have a problem with state machine, witch will use for calculating... this is how should it look.

    [​IMG]
    By goranbm

    When i am in state one, i enter numbers from keyboard , in code it is variable Numbers . then when i press one of this letters (Z, O, M, D, it is letters for mathematical operations) i need to jump to state two, and save my first number in reg A, and to reset Numbers, then when i am in state two, i need to enter second number from keyboard, then i press enter, second number is saved in reg B, and i get on the display the result of operation, /, *, + or -, ofcourse when we jump from sate one, to state two, we declare our operation....

    This is main part of my code....

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity keyboardVhdl is
    Port ( CLK, RST, KD, KC: in std_logic;
    Digits : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    minus : out std_logic);


    end keyboardVhdl;


    architecture Behavioral of keyboardVhdl is

    ------------------------------------------------------------------------
    -- Component Declarations
    ------------------------------------------------------------------------

    ------------------------------------------------------------------------
    -- Signal Declarations
    ------------------------------------------------------------------------
    signal clkDiv : std_logic_vector (3 downto 0);
    signal pclk : std_logic;
    signal KDI, KCI : std_logic;
    signal DFF1, DFF2 : std_logic;
    signal shiftRegSig1: std_logic_vector(10 downto 0);
    signal shiftRegSig2: std_logic_vector(10 downto 1);
    signal iDigits : std_logic_vector(15 downto 0);
    signal iOperacija : std_logic_vector(3 downto 0);
    signal iEnter : std_logic_vector(3 downto 0);
    signal A, B, S, R : std_logic_vector(15 downto 0);
    type state is (PRVIBROJ, DRUGIBROJ, REZULTAT);
    signal pr_state, nx_state : state;

    ------------------------------------------------------------------------
    -- Module Implementation
    ------------------------------------------------------------------------

    begin
    --Divide the master clock down to a lower frequency--
    CLKDivider: Process (CLK)
    begin
    if (CLK = '1' and CLK'Event) then
    clkDiv <= clkDiv +1;
    end if;
    end Process;

    pclk <= clkDiv(3);

    --Flip Flops used to condition siglans coming from PS2--
    Process (pclk, RST, KC, KD)
    begin
    if(RST = '1') then
    DFF1 <= '0'; DFF2 <= '0'; KDI <= '0'; KCI <= '0';
    else
    if (pclk = '1' and pclk'Event) then
    DFF1 <= KD; KDI <= DFF1; DFF2 <= KC; KCI <= DFF2;
    end if;
    end if;
    end process;

    --Shift Registers used to clock in scan codes from PS2--
    Process(KDI, KCI, RST) --DFF2 carries KD and DFF4, and DFF4 carries KC
    begin
    if (RST = '1') then
    ShiftRegSig1 <= "00000000000";
    ShiftRegSig2 <= "0000000000";
    else
    if (KCI = '0' and KCI'Event) then
    ShiftRegSig1(10 downto 0) <= KDI & ShiftRegSig1(10 downto 1);
    ShiftRegSig2(10 downto 1) <= ShiftRegSig1(0) & ShiftRegSig2(10 downto 2);
    end if;
    end if;
    end process;

    --Wait Register
    process(ShiftRegSig1, ShiftRegSig2, RST, KCI)
    VARIABLE Number : STD_LOGIC_VECTOR(3 DOWNTO 0);
    VARIABLE Numbers : STD_LOGIC_VECTOR(15 DOWNTO 0);
    VARIABLE Operacija : STD_LOGIC_VECTOR(3 DOWNTO 0);
    VARIABLE Enter : STD_LOGIC_VECTOR(3 DOWNTO 0);
    begin
    if(RST = '1')then
    Number := (OTHERS => '0');
    Numbers := (OTHERS => '0');
    else
    if(KCI'event and KCI = '1' and ShiftRegSig2(8 downto 1) = "11110000")then
    Case ShiftRegSig1(8 downto 1) is
    when X"45" =>
    Number := "0000";
    Operacija := "0000";
    when X"16" =>
    Number := "0001";
    Operacija := "0000";
    when X"1E" =>
    Number := "0010";
    Operacija := "0000";
    when X"26" =>
    Number := "0011";
    Operacija := "0000";
    when X"25" =>
    Number := "0100";
    Operacija := "0000";
    when X"2E" =>
    Number := "0101";
    Operacija := "0000";
    when X"36" =>
    Number := "0110";
    Operacija := "0000";
    when X"3D" =>
    Number := "0111";
    Operacija := "0000";
    when X"3E" =>
    Number := "1000";
    Operacija := "0000";
    when X"46" =>
    Number := "1001";
    Operacija := "0000";
    when X"35" =>
    Operacija := "0001";
    Number := "0000";
    when X"44" =>
    Operacija := "0010";
    Number := "0000";
    when X"3A" =>
    Operacija := "0100";
    Number := "0000";
    when X"23" =>
    Operacija := "1000";
    Number := "0000";
    when X"5A" =>
    Operacija := "1001";
    Number := "0000";
    when Others =>
    Number := "1111";
    end case;
    if (Operacija /= "0000") then
    iA <= Numbers;
    Numbers := (others => '0');
    else
    Numbers := Numbers(11 DOWNTO 0) & Number;
    end if;
    end if;
    iDigits <= Numbers;
    iOperacija <= Operacija;
    end if;
    end Process;


    Digits <= iDigits;

    process (rst)
    begin
    if (rst = '1') then
    pr_state <= PRVIBROJ;
    end if;
    end process;
    -----Gornji dio----------
    process (pr_state, rst)
    begin
    case pr_state is
    when PRVIBROJ =>
    if (iOperacija /= "0000") then
    A <= iDigits;
    nx_state <= DRUGIBROJ;
    else
    nx_state <= PRVIBROJ;
    end if;
    when DRUGIBROJ =>
    if (iEnter /= "0000") then
    B <= iDigits;
    nx_state <= REZULTAT;
    else
    nx_state <= DRUGIBROJ;
    end if;
    when REZULTAT =>
    if (iOperacija = "0001") then
    R <= A+B;
    elsif (iOperacija /= "0010") then
    if (A >= B) then
    R <= A-B;
    minus <= '0';
    else
    R <=B-A;
    minus <= '1';
    end if;
    elsif (iOperacija /= "0100") then
    R <= A*B;
    elsif (iOperacija /= "1000") then
    R <= A and B;
    end if;
    end case;
    end process;


    Red part represents entering numbers from keyboard, and the blue part is attempt of my state machine , and it is not good, please can you help me, and write me a part that im am mising, please i am desperate... thanks in advance....
     
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